upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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596 lines
15 KiB
596 lines
15 KiB
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/inca-ip.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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typedef unsigned long FLASH_PORT_WIDTH;
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typedef volatile unsigned long FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0xFFFFFFFF
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define ORMASK(size) ((-size) & OR_AM_MSK)
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#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
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/* FLASH29 command register addresses */
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#define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555)
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#define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa)
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#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555)
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#define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555)
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#define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa)
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#define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555)
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/* FLASH29 command definitions */
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#define FLASH29_CMD_FIRST 0xaaaaaaaa
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#define FLASH29_CMD_SECOND 0x55555555
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#define FLASH29_CMD_FOURTH 0xaaaaaaaa
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#define FLASH29_CMD_FIFTH 0x55555555
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#define FLASH29_CMD_SIXTH 0x10101010
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#define FLASH29_CMD_SECTOR 0x30303030
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#define FLASH29_CMD_PROGRAM 0xa0a0a0a0
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#define FLASH29_CMD_CHIP_ERASE 0x80808080
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#define FLASH29_CMD_READ_RESET 0xf0f0f0f0
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#define FLASH29_CMD_AUTOSELECT 0x90909090
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#define FLASH29_CMD_READ 0x70707070
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#define IN_RAM_CMD_READ 0x1
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#define IN_RAM_CMD_WRITE 0x2
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#define FLASH_WRITE_CMD ((ulong)(flash_write_cmd) & 0x7)+0xbf008000
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#define FLASH_READ_CMD ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
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typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
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typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
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typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
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static ulong flash_get_size(FPWV *addr, flash_info_t *info);
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static int write_word(flash_info_t *info, FPWV *dest, FPW data);
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static void flash_get_offsets(ulong base, flash_info_t *info);
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static flash_info_t *flash_get_info(ulong base);
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static void load_cmd(ulong cmd);
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static ulong in_ram_cmd = 0;
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/******************************************************************************
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*
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* Don't change the program architecture
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* This architecture assure the program
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* can be relocated to scratch ram
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*/
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static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
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{
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int i,j;
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FPW temp,temp1;
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FPWV *str;
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str = (FPWV *)string;
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j= strLen/4;
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if(cmd == FLASH29_CMD_AUTOSELECT)
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{
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*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
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*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT;
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}
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if(cmd == FLASH29_CMD_READ)
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{
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i = 0;
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while(i<j)
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{
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temp = *pFA++;
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temp1 = *(int *)0xa0000000;
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*(int *)0xbf0081f8 = temp1 + temp;
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*str++ = temp;
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i++;
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}
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}
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if(cmd == FLASH29_CMD_READ_RESET)
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{
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*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
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*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
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}
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*(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
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}
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/******************************************************************************
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*
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* Don't change the program architecture
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* This architecture assure the program
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* can be relocated to scratch ram
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*/
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static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
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{
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*(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
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*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
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if (cmd == FLASH29_CMD_SECTOR)
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{
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
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*(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
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*(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
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*pFA = FLASH29_CMD_SECTOR;
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}
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if (cmd == FLASH29_CMD_SIXTH)
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{
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
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*(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
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*(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
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*(FLASH29_REG_SIXTH_CYCLE) = FLASH29_CMD_SIXTH;
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}
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if (cmd == FLASH29_CMD_PROGRAM)
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{
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_PROGRAM;
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*pFA = value;
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}
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if (cmd == FLASH29_CMD_READ_RESET)
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{
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*(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
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}
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*(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
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}
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static void load_cmd(ulong cmd)
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{
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ulong *src;
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ulong *dst;
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FUNCPTR_CP absEntry;
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ulong func;
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if (in_ram_cmd & cmd) return;
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if (cmd == IN_RAM_CMD_READ)
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{
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func = (ulong)flash_read_cmd;
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}
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else
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{
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func = (ulong)flash_write_cmd;
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}
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src = (ulong *)(func & 0xfffffff8);
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dst = (ulong *)0xbf008000;
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absEntry = (FUNCPTR_CP)(0xbf0081d0);
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absEntry(src,dst,0x38);
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in_ram_cmd = cmd;
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}
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init (void)
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{
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unsigned long size = 0;
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int i;
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load_cmd(IN_RAM_CMD_READ);
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/* Init: no FLASHes known */
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for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
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ulong flashbase = PHYS_FLASH_1;
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ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
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/* Disable write protection */
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*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
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#if 1
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memset(&flash_info[i], 0, sizeof(flash_info_t));
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#endif
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flash_info[i].size =
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flash_get_size((FPW *)flashbase, &flash_info[i]);
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
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i, flash_info[i].size);
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}
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size += flash_info[i].size;
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}
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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flash_get_info(CFG_MONITOR_BASE));
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR+CFG_ENV_SIZE-1,
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flash_get_info(CFG_ENV_ADDR));
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#endif
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return size;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info)
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{
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int i;
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
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&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) {
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int bootsect_size[4]; /* number of bytes/boot sector */
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int sect_size; /* number of bytes/regular sector */
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bootsect_size[0] = 0x00008000;
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bootsect_size[1] = 0x00004000;
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bootsect_size[2] = 0x00004000;
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bootsect_size[3] = 0x00010000;
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sect_size = 0x00020000;
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/* set sector offsets for bottom boot block type */
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] = base;
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base += i < 4 ? bootsect_size[i] : sect_size;
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}
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}
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}
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/*-----------------------------------------------------------------------
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*/
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static flash_info_t *flash_get_info(ulong base)
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{
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int i;
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flash_info_t * info;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
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info = & flash_info[i];
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if (info->start[0] <= base && base < info->start[0] + info->size)
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break;
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}
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return i == CFG_MAX_FLASH_BANKS ? 0 : info;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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uchar *boottype;
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uchar *bootletter;
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uchar *fmt;
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uchar botbootletter[] = "B";
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uchar topbootletter[] = "T";
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uchar botboottype[] = "bottom boot sector";
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uchar topboottype[] = "top boot sector";
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_SST: printf ("SST "); break;
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case FLASH_MAN_STM: printf ("STM "); break;
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case FLASH_MAN_INTEL: printf ("INTEL "); break;
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default: printf ("Unknown Vendor "); break;
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}
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/* check for top or bottom boot, if it applies */
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if (info->flash_id & FLASH_BTYPE) {
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boottype = botboottype;
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bootletter = botbootletter;
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}
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else {
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boottype = topboottype;
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bootletter = topbootletter;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM160B:
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fmt = "29LV160B%s (16 Mbit, %s)\n";
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break;
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case FLASH_28F800C3B:
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case FLASH_28F800C3T:
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fmt = "28F800C3%s (8 Mbit, %s)\n";
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break;
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case FLASH_INTEL800B:
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case FLASH_INTEL800T:
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fmt = "28F800B3%s (8 Mbit, %s)\n";
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break;
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case FLASH_28F160C3B:
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case FLASH_28F160C3T:
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fmt = "28F160C3%s (16 Mbit, %s)\n";
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break;
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case FLASH_INTEL160B:
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case FLASH_INTEL160T:
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fmt = "28F160B3%s (16 Mbit, %s)\n";
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break;
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case FLASH_28F320C3B:
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case FLASH_28F320C3T:
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fmt = "28F320C3%s (32 Mbit, %s)\n";
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break;
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case FLASH_INTEL320B:
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case FLASH_INTEL320T:
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fmt = "28F320B3%s (32 Mbit, %s)\n";
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break;
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case FLASH_28F640C3B:
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case FLASH_28F640C3T:
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fmt = "28F640C3%s (64 Mbit, %s)\n";
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break;
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case FLASH_INTEL640B:
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case FLASH_INTEL640T:
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fmt = "28F640B3%s (64 Mbit, %s)\n";
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break;
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default:
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fmt = "Unknown Chip Type\n";
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break;
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}
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printf (fmt, bootletter, boottype);
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20,
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info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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}
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size (FPWV *addr, flash_info_t *info)
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{
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FUNCPTR_RD absEntry;
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FPW retValue;
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int flag;
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load_cmd(IN_RAM_CMD_READ);
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absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
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flag = disable_interrupts();
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absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
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if (flag) enable_interrupts();
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udelay(100);
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flag = disable_interrupts();
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absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue));
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absEntry(FLASH29_CMD_READ_RESET,0,0,0);
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if (flag) enable_interrupts();
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udelay(100);
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switch (retValue) {
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case (FPW)AMD_ID_LV160B:
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00400000;
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break; /* => 8 or 16 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* => no or unknown flash */
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}
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flash_get_offsets((ulong)addr, info);
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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FPWV *addr;
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int flag, prot, sect;
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ulong start, now, last;
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int rcode = 0;
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FUNCPTR_WR absEntry;
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load_cmd(IN_RAM_CMD_WRITE);
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absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM160B:
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break;
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case FLASH_UNKNOWN:
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default:
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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last = get_timer(0);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
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if (info->protect[sect] != 0) /* protected, skip it */
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continue;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr = (FPWV *)(info->start[sect]);
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absEntry(FLASH29_CMD_SECTOR, addr, 0);
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer(0);
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while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) {
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|
|
/* show that we're waiting */
|
|
if ((get_timer(last)) > CFG_HZ) {/* every second */
|
|
putc ('.');
|
|
last = get_timer(0);
|
|
}
|
|
}
|
|
|
|
flag = disable_interrupts();
|
|
absEntry(FLASH29_CMD_READ_RESET,0,0);
|
|
if (flag)
|
|
enable_interrupts();
|
|
}
|
|
|
|
printf (" done\n");
|
|
return rcode;
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* Copy memory to flash, returns:
|
|
* 0 - OK
|
|
* 1 - write timeout
|
|
* 2 - Flash not erased
|
|
*/
|
|
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
{
|
|
FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
|
|
int bytes; /* number of bytes to program in current word */
|
|
int left; /* number of bytes left to program */
|
|
int i, res;
|
|
|
|
for (left = cnt, res = 0;
|
|
left > 0 && res == 0;
|
|
addr += sizeof(data), left -= sizeof(data) - bytes) {
|
|
|
|
bytes = addr & (sizeof(data) - 1);
|
|
addr &= ~(sizeof(data) - 1);
|
|
|
|
/* combine source and destination data so can program
|
|
* an entire word of 16 or 32 bits
|
|
*/
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
data <<= 8;
|
|
if (i < bytes || i - bytes >= left )
|
|
data += *((uchar *)addr + i);
|
|
else
|
|
data += *src++;
|
|
}
|
|
|
|
res = write_word(info, (FPWV *)addr, data);
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
static int write_word (flash_info_t *info, FPWV *dest, FPW data)
|
|
{
|
|
int res = 0; /* result, assume success */
|
|
FUNCPTR_WR absEntry;
|
|
int flag;
|
|
|
|
/* Check if Flash is (sufficiently) erased */
|
|
if ((*dest & data) != data) {
|
|
return (2);
|
|
}
|
|
|
|
if (info->start[0] != PHYS_FLASH_1)
|
|
{
|
|
return (3);
|
|
}
|
|
|
|
load_cmd(IN_RAM_CMD_WRITE);
|
|
absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
|
|
|
|
flag = disable_interrupts();
|
|
absEntry(FLASH29_CMD_PROGRAM,dest,data);
|
|
if (flag) enable_interrupts();
|
|
|
|
udelay(100);
|
|
|
|
flag = disable_interrupts();
|
|
absEntry(FLASH29_CMD_READ_RESET,0,0);
|
|
if (flag) enable_interrupts();
|
|
|
|
return (res);
|
|
}
|
|
|