upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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130 lines
3.1 KiB
130 lines
3.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Tests for the driver model pmic API
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*
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* Copyright (c) 2015 Samsung Electronics
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* Przemyslaw Marczak <p.marczak@samsung.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <dm/device-internal.h>
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#include <dm/root.h>
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#include <dm/util.h>
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#include <dm/test.h>
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#include <dm/uclass-internal.h>
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#include <power/pmic.h>
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#include <power/sandbox_pmic.h>
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#include <test/ut.h>
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#include <fsl_pmic.h>
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/* Test PMIC get method */
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static inline int power_pmic_get(struct unit_test_state *uts, char *name)
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{
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struct udevice *dev;
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ut_assertok(pmic_get(name, &dev));
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ut_assertnonnull(dev);
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/* Check PMIC's name */
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ut_asserteq_str(name, dev->name);
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return 0;
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}
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/* Test PMIC get method */
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static int dm_test_power_pmic_get(struct unit_test_state *uts)
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{
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power_pmic_get(uts, "sandbox_pmic");
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return 0;
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}
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DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
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/* PMIC get method - MC34708 - for 3 bytes transmission */
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static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
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{
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power_pmic_get(uts, "pmic@41");
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
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/* Test PMIC I/O */
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static int dm_test_power_pmic_io(struct unit_test_state *uts)
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{
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const char *name = "sandbox_pmic";
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uint8_t out_buffer, in_buffer;
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struct udevice *dev;
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int reg_count, i;
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ut_assertok(pmic_get(name, &dev));
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reg_count = pmic_reg_count(dev);
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ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
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/*
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* Test PMIC I/O - write and read a loop counter.
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* usually we can't write to all PMIC's registers in the real hardware,
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* but we can to the sandbox pmic.
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*/
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for (i = 0; i < reg_count; i++) {
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out_buffer = i;
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ut_assertok(pmic_write(dev, i, &out_buffer, 1));
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ut_assertok(pmic_read(dev, i, &in_buffer, 1));
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ut_asserteq(out_buffer, in_buffer);
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}
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return 0;
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}
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DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
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#define MC34708_PMIC_REG_COUNT 64
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#define MC34708_PMIC_TEST_VAL 0x125534
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static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
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{
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struct udevice *dev;
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int reg_count;
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ut_assertok(pmic_get("pmic@41", &dev));
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/* Check number of PMIC registers */
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reg_count = pmic_reg_count(dev);
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ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
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static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
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{
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struct udevice *dev;
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int val;
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ut_assertok(pmic_get("pmic@41", &dev));
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/* Check if single 3 byte read is successful */
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val = pmic_reg_read(dev, REG_POWER_CTL2);
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ut_asserteq(val, 0x422100);
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/* Check if RW works */
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val = 0;
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ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
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ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
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val = pmic_reg_read(dev, REG_RTC_TIME);
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ut_asserteq(val, MC34708_PMIC_TEST_VAL);
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pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
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val = pmic_reg_read(dev, REG_POWER_CTL2);
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ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
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return 0;
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}
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DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);
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