upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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521 lines
14 KiB
521 lines
14 KiB
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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/*
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* Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
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* Based on code from spd_sdram.c
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* Author: James Yang [at freescale.com]
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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extern void fsl_ddr_set_lawbar(
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const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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/* processor specific function */
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extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num);
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/* Board-specific functions defined in each board's ddr.c */
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extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num);
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/*
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* ASSUMPTIONS:
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* - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
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* - Same memory data bus width on all controllers
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*
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* NOTES:
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*
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* The memory controller and associated documentation use confusing
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* terminology when referring to the orgranization of DRAM.
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*
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* Here is a terminology translation table:
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*
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* memory controller/documention |industry |this code |signals
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* -------------------------------|-----------|-----------|-----------------
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* physical bank/bank |rank |rank |chip select (CS)
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* logical bank/sub-bank |bank |bank |bank address (BA)
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* page/row |row |page |row address
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* ??? |column |column |column address
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*
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* The naming confusion is further exacerbated by the descriptions of the
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* memory controller interleaving feature, where accesses are interleaved
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* _BETWEEN_ two seperate memory controllers. This is configured only in
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* CS0_CONFIG[INTLV_CTL] of each memory controller.
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*
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* memory controller documentation | number of chip selects
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* | per memory controller supported
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* --------------------------------|-----------------------------------------
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* cache line interleaving | 1 (CS0 only)
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* page interleaving | 1 (CS0 only)
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* bank interleaving | 1 (CS0 only)
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* superbank interleraving | depends on bank (chip select)
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* | interleraving [rank interleaving]
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* | mode used on every memory controller
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*
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* Even further confusing is the existence of the interleaving feature
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* _WITHIN_ each memory controller. The feature is referred to in
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* documentation as chip select interleaving or bank interleaving,
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* although it is configured in the DDR_SDRAM_CFG field.
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*
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* Name of field | documentation name | this code
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* -----------------------------|-----------------------|------------------
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* DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
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* | interleaving
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*/
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#ifdef DEBUG
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const char *step_string_tbl[] = {
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"STEP_GET_SPD",
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"STEP_COMPUTE_DIMM_PARMS",
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"STEP_COMPUTE_COMMON_PARMS",
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"STEP_GATHER_OPTS",
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"STEP_ASSIGN_ADDRESSES",
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"STEP_COMPUTE_REGS",
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"STEP_PROGRAM_REGS",
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"STEP_ALL"
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};
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const char * step_to_string(unsigned int step) {
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unsigned int s = __ilog2(step);
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if ((1 << s) != step)
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return step_string_tbl[7];
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return step_string_tbl[s];
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}
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#endif
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int step_assign_addresses(fsl_ddr_info_t *pinfo,
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unsigned int dbw_cap_adj[],
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unsigned int *memctl_interleaving,
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unsigned int *rank_interleaving)
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{
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int i, j;
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/*
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* If a reduced data width is requested, but the SPD
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* specifies a physically wider device, adjust the
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* computed dimm capacities accordingly before
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* assigning addresses.
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*/
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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unsigned int found = 0;
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switch (pinfo->memctl_opts[i].data_bus_width) {
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case 2:
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/* 16-bit */
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printf("can't handle 16-bit mode yet\n");
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break;
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case 1:
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/* 32-bit */
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned int dw;
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dw = pinfo->dimm_params[i][j].data_width;
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if (pinfo->dimm_params[i][j].n_ranks
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&& (dw == 72 || dw == 64)) {
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/*
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* FIXME: can't really do it
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* like this because this just
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* further reduces the memory
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*/
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found = 1;
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break;
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}
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}
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if (found) {
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dbw_cap_adj[i] = 1;
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}
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break;
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case 0:
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/* 64-bit */
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break;
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default:
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printf("unexpected data bus width "
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"specified controller %u\n", i);
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return 1;
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}
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}
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/*
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* Check if all controllers are configured for memory
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* controller interleaving.
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*/
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j = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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if (pinfo->memctl_opts[i].memctl_interleaving) {
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j++;
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}
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}
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if (j == 2) {
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*memctl_interleaving = 1;
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printf("\nMemory controller interleaving enabled: ");
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switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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printf("Cache-line interleaving!\n");
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break;
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case FSL_DDR_PAGE_INTERLEAVING:
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printf("Page interleaving!\n");
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break;
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case FSL_DDR_BANK_INTERLEAVING:
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printf("Bank interleaving!\n");
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break;
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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printf("Super bank interleaving\n");
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default:
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break;
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}
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}
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/* Check that all controllers are rank interleaving. */
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j = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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if (pinfo->memctl_opts[i].ba_intlv_ctl) {
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j++;
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}
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}
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if (j == 2) {
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*rank_interleaving = 1;
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printf("Bank(chip-select) interleaving enabled: ");
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switch (pinfo->memctl_opts[0].ba_intlv_ctl &
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FSL_DDR_CS0_CS1_CS2_CS3) {
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case FSL_DDR_CS0_CS1_CS2_CS3:
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printf("CS0+CS1+CS2+CS3\n");
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break;
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case FSL_DDR_CS0_CS1:
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printf("CS0+CS1\n");
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break;
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case FSL_DDR_CS2_CS3:
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printf("CS2+CS3\n");
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break;
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case FSL_DDR_CS0_CS1_AND_CS2_CS3:
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printf("CS0+CS1 and CS2+CS3\n");
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default:
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break;
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}
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}
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if (*memctl_interleaving) {
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phys_addr_t addr;
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phys_size_t total_mem_per_ctlr = 0;
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/*
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* If interleaving between memory controllers,
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* make each controller start at a base address
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* of 0.
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*
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* Also, if bank interleaving (chip select
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* interleaving) is enabled on each memory
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* controller, CS0 needs to be programmed to
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* cover the entire memory range on that memory
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* controller
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*
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* Bank interleaving also implies that each
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* addressed chip select is identical in size.
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*/
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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addr = 0;
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pinfo->common_timing_params[i].base_address =
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(phys_addr_t)addr;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned long long cap
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= pinfo->dimm_params[i][j].capacity;
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pinfo->dimm_params[i][j].base_address = addr;
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addr += (phys_addr_t)(cap >> dbw_cap_adj[i]);
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total_mem_per_ctlr += cap >> dbw_cap_adj[i];
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}
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}
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pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
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} else {
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/*
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* Simple linear assignment if memory
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* controllers are not interleaved.
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*/
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phys_size_t cur_memsize = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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phys_size_t total_mem_per_ctlr = 0;
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pinfo->common_timing_params[i].base_address =
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(phys_addr_t)cur_memsize;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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/* Compute DIMM base addresses. */
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unsigned long long cap =
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pinfo->dimm_params[i][j].capacity;
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pinfo->dimm_params[i][j].base_address =
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(phys_addr_t)cur_memsize;
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cur_memsize += cap >> dbw_cap_adj[i];
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total_mem_per_ctlr += cap >> dbw_cap_adj[i];
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}
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pinfo->common_timing_params[i].total_mem =
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total_mem_per_ctlr;
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}
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}
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return 0;
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}
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phys_size_t
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fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
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{
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unsigned int i, j;
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unsigned int all_controllers_memctl_interleaving = 0;
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unsigned int all_controllers_rank_interleaving = 0;
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phys_size_t total_mem = 0;
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fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
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common_timing_params_t *timing_params = pinfo->common_timing_params;
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/* data bus width capacity adjust shift amount */
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unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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dbw_capacity_adjust[i] = 0;
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}
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debug("starting at step %u (%s)\n",
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start_step, step_to_string(start_step));
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switch (start_step) {
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case STEP_GET_SPD:
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/* STEP 1: Gather all DIMM SPD data */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
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}
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case STEP_COMPUTE_DIMM_PARMS:
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/* STEP 2: Compute DIMM parameters from SPD data */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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unsigned int retval;
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generic_spd_eeprom_t *spd =
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&(pinfo->spd_installed_dimms[i][j]);
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dimm_params_t *pdimm =
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&(pinfo->dimm_params[i][j]);
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retval = compute_dimm_parameters(spd, pdimm, i);
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if (retval == 2) {
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printf("Error: compute_dimm_parameters"
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" non-zero returned FATAL value "
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"for memctl=%u dimm=%u\n", i, j);
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return 0;
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}
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if (retval) {
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debug("Warning: compute_dimm_parameters"
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" non-zero return value for memctl=%u "
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"dimm=%u\n", i, j);
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}
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}
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}
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case STEP_COMPUTE_COMMON_PARMS:
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/*
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* STEP 3: Compute a common set of timing parameters
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* suitable for all of the DIMMs on each memory controller
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*/
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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debug("Computing lowest common DIMM"
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" parameters for memctl=%u\n", i);
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compute_lowest_common_dimm_parameters(
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pinfo->dimm_params[i],
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&timing_params[i],
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CONFIG_DIMM_SLOTS_PER_CTLR);
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}
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case STEP_GATHER_OPTS:
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/* STEP 4: Gather configuration requirements from user */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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debug("Reloading memory controller "
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"configuration options for memctl=%u\n", i);
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/*
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* This "reloads" the memory controller options
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* to defaults. If the user "edits" an option,
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* next_step points to the step after this,
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* which is currently STEP_ASSIGN_ADDRESSES.
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*/
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populate_memctl_options(
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timing_params[i].all_DIMMs_registered,
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&pinfo->memctl_opts[i],
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pinfo->dimm_params[i], i);
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}
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case STEP_ASSIGN_ADDRESSES:
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/* STEP 5: Assign addresses to chip selects */
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step_assign_addresses(pinfo,
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dbw_capacity_adjust,
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&all_controllers_memctl_interleaving,
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&all_controllers_rank_interleaving);
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case STEP_COMPUTE_REGS:
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/* STEP 6: compute controller register values */
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debug("FSL Memory ctrl cg register computation\n");
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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if (timing_params[i].ndimms_present == 0) {
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memset(&ddr_reg[i], 0,
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sizeof(fsl_ddr_cfg_regs_t));
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continue;
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}
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compute_fsl_memctl_config_regs(
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&pinfo->memctl_opts[i],
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&ddr_reg[i], &timing_params[i],
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pinfo->dimm_params[i],
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dbw_capacity_adjust[i]);
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}
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default:
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break;
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}
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/* Compute the total amount of memory. */
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/*
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* If bank interleaving but NOT memory controller interleaving
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* CS_BNDS describe the quantity of memory on each memory
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* controller, so the total is the sum across.
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*/
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if (!all_controllers_memctl_interleaving
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&& all_controllers_rank_interleaving) {
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total_mem = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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total_mem += timing_params[i].total_mem;
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}
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} else {
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/*
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* Compute the amount of memory available just by
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* looking for the highest valid CSn_BNDS value.
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* This allows us to also experiment with using
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* only CS0 when using dual-rank DIMMs.
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*/
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unsigned int max_end = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
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fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
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if (reg->cs[j].config & 0x80000000) {
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unsigned int end;
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end = reg->cs[j].bnds & 0xFFF;
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if (end > max_end) {
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max_end = end;
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}
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}
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}
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}
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#if !defined(CONFIG_PHYS_64BIT)
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/* Check for 4G or more with a 32-bit phys_addr_t. Bad. */
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if (max_end >= 0xff) {
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printf("This U-Boot only supports < 4G of DDR\n");
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printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
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return 0; /* Ensure DDR setup failure. */
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}
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#endif
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total_mem = 1 + (((unsigned long long)max_end << 24ULL)
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| 0xFFFFFFULL);
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}
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return total_mem;
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}
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/*
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* fsl_ddr_sdram() -- this is the main function to be called by
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* initdram() in the board file.
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*
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* It returns amount of memory configured in bytes.
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*/
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phys_size_t fsl_ddr_sdram(void)
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{
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unsigned int i;
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unsigned int memctl_interleaved;
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phys_size_t total_memory;
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fsl_ddr_info_t info;
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/* Reset info structure. */
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memset(&info, 0, sizeof(fsl_ddr_info_t));
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/* Compute it once normally. */
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total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
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/* Check for memory controller interleaving. */
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memctl_interleaved = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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memctl_interleaved +=
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info.memctl_opts[i].memctl_interleaving;
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}
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if (memctl_interleaved) {
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if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
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debug("memctl interleaving\n");
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/*
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* Change the meaning of memctl_interleaved
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* to be "boolean".
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*/
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memctl_interleaved = 1;
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} else {
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printf("Warning: memctl interleaving not "
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"properly configured on all controllers\n");
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memctl_interleaved = 0;
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
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info.memctl_opts[i].memctl_interleaving = 0;
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debug("Recomputing with memctl_interleaving off.\n");
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total_memory = fsl_ddr_compute(&info,
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STEP_ASSIGN_ADDRESSES);
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}
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}
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/* Program configuration registers. */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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debug("Programming controller %u\n", i);
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if (info.common_timing_params[i].ndimms_present == 0) {
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debug("No dimms present on controller %u; "
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"skipping programming\n", i);
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continue;
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}
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fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
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|
}
|
|
|
|
if (memctl_interleaved) {
|
|
const unsigned int ctrl_num = 0;
|
|
|
|
/* Only set LAWBAR1 if memory controller interleaving is on. */
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[0],
|
|
memctl_interleaved, ctrl_num);
|
|
} else {
|
|
/*
|
|
* Memory controller interleaving is NOT on;
|
|
* set each lawbar individually.
|
|
*/
|
|
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
|
fsl_ddr_set_lawbar(&info.common_timing_params[i],
|
|
0, i);
|
|
}
|
|
}
|
|
|
|
debug("total_memory = %llu\n", (u64)total_memory);
|
|
|
|
return total_memory;
|
|
}
|
|
|