upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
1.9 KiB
71 lines
1.9 KiB
/*
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* (C) Copyright 2010,2011
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* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARMV7M_H
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#define ARMV7M_H
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#if defined(__ASSEMBLY__)
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.syntax unified
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.thumb
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#endif
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#define V7M_SCB_BASE 0xE000ED00
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#define V7M_MPU_BASE 0xE000ED90
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#define V7M_SCB_VTOR 0x08
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#if !defined(__ASSEMBLY__)
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struct v7m_scb {
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uint32_t cpuid; /* CPUID Base Register */
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uint32_t icsr; /* Interrupt Control and State Register */
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uint32_t vtor; /* Vector Table Offset Register */
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uint32_t aircr; /* App Interrupt and Reset Control Register */
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};
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#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE)
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#define V7M_AIRCR_VECTKEY 0x5fa
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#define V7M_AIRCR_VECTKEY_SHIFT 16
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#define V7M_AIRCR_ENDIAN (1 << 15)
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#define V7M_AIRCR_PRIGROUP_SHIFT 8
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#define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
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#define V7M_AIRCR_SYSRESET (1 << 2)
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#define V7M_ICSR_VECTACT_MSK 0xFF
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struct v7m_mpu {
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uint32_t type; /* Type Register */
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uint32_t ctrl; /* Control Register */
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uint32_t rnr; /* Region Number Register */
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uint32_t rbar; /* Region Base Address Register */
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uint32_t rasr; /* Region Attribute and Size Register */
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};
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#define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE)
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#define V7M_MPU_CTRL_ENABLE (1 << 0)
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#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
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#define V7M_MPU_CTRL_ENABLE (1 << 0)
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#define V7M_MPU_CTRL_DISABLE (0 << 0)
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#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
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#define V7M_MPU_RASR_EN (1 << 0)
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#define V7M_MPU_RASR_SIZE_BITS 1
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#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS)
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#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS)
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#define V7M_MPU_RASR_TEX_SHIFT 19
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#define V7M_MPU_RASR_S_SHIFT 18
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#define V7M_MPU_RASR_C_SHIFT 17
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#define V7M_MPU_RASR_B_SHIFT 16
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#define V7M_MPU_RASR_AP_RW_RW (3 << 24)
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#define V7M_MPU_RASR_XN_ENABLE (0 << 28)
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#define V7M_MPU_RASR_XN_DISABLE (1 << 28)
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#endif /* !defined(__ASSEMBLY__) */
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#endif /* ARMV7M_H */
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