upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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533 lines
15 KiB
533 lines
15 KiB
/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from Intel released Quark UEFI BIOS
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* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef _SMC_H_
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#define _SMC_H_
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/* System Memory Controller Register Defines */
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/* Memory Controller Message Bus Registers Offsets */
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#define DRP 0x00
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#define DTR0 0x01
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#define DTR1 0x02
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#define DTR2 0x03
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#define DTR3 0x04
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#define DTR4 0x05
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#define DPMC0 0x06
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#define DPMC1 0x07
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#define DRFC 0x08
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#define DSCH 0x09
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#define DCAL 0x0a
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#define DRMC 0x0b
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#define PMSTS 0x0c
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#define DCO 0x0f
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#define DSTAT 0x20
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#define SSKPD0 0x4a
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#define SSKPD1 0x4b
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#define DECCCTRL 0x60
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#define DECCSTAT 0x61
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#define DECCSBECNT 0x62
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#define DECCSBECA 0x68
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#define DECCSBECS 0x69
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#define DECCDBECA 0x6a
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#define DECCDBECS 0x6b
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#define DFUSESTAT 0x70
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#define SCRMSEED 0x80
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#define SCRMLO 0x81
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#define SCRMHI 0x82
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/* DRP register defines */
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#define DRP_RKEN0 (1 << 0)
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#define DRP_RKEN1 (1 << 1)
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#define DRP_PRI64BSPLITEN (1 << 13)
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#define DRP_ADDRMAP_MAP0 (1 << 14)
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#define DRP_ADDRMAP_MAP1 (1 << 15)
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#define DRP_ADDRMAP_MASK 0x0000c000
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/* DTR0 register defines */
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#define DTR0_DFREQ_MASK 0x00000003
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#define DTR0_TRP_MASK 0x000000f0
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#define DTR0_TRCD_MASK 0x00000f00
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#define DTR0_TCL_MASK 0x00007000
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/* DTR1 register defines */
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#define DTR1_TWCL_MASK 0x00000007
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#define DTR1_TCMD_MASK 0x00000030
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#define DTR1_TWTP_MASK 0x00000f00
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#define DTR1_TCCD_12CLK (1 << 12)
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#define DTR1_TCCD_18CLK (1 << 13)
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#define DTR1_TCCD_MASK 0x00003000
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#define DTR1_TFAW_MASK 0x000f0000
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#define DTR1_TRAS_MASK 0x00f00000
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#define DTR1_TRRD_MASK 0x03000000
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#define DTR1_TRTP_MASK 0x70000000
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/* DTR2 register defines */
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#define DTR2_TRRDR_MASK 0x00000007
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#define DTR2_TWWDR_MASK 0x00000700
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#define DTR2_TRWDR_MASK 0x000f0000
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/* DTR3 register defines */
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#define DTR3_TWRDR_MASK 0x00000007
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#define DTR3_TXXXX_MASK 0x00000070
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#define DTR3_TRWSR_MASK 0x00000f00
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#define DTR3_TWRSR_MASK 0x0001e000
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#define DTR3_TXP_MASK 0x00c00000
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/* DTR4 register defines */
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#define DTR4_WRODTSTRT_MASK 0x00000003
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#define DTR4_WRODTSTOP_MASK 0x00000070
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#define DTR4_XXXX1_MASK 0x00000700
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#define DTR4_XXXX2_MASK 0x00007000
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#define DTR4_ODTDIS (1 << 15)
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#define DTR4_TRGSTRDIS (1 << 16)
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/* DPMC0 register defines */
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#define DPMC0_PCLSTO_MASK 0x00070000
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#define DPMC0_PREAPWDEN (1 << 21)
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#define DPMC0_DYNSREN (1 << 23)
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#define DPMC0_CLKGTDIS (1 << 24)
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#define DPMC0_DISPWRDN (1 << 25)
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#define DPMC0_ENPHYCLKGATE (1 << 29)
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/* DRFC register defines */
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#define DRFC_TREFI_MASK 0x00007000
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#define DRFC_REFDBTCLR (1 << 21)
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/* DSCH register defines */
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#define DSCH_OOODIS (1 << 8)
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#define DSCH_OOOST3DIS (1 << 9)
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#define DSCH_NEWBYPDIS (1 << 12)
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/* DCAL register defines */
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#define DCAL_ZQCINT_MASK 0x00000700
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#define DCAL_SRXZQCL_MASK 0x00003000
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/* DRMC register defines */
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#define DRMC_CKEMODE (1 << 4)
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#define DRMC_ODTMODE (1 << 12)
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#define DRMC_COLDWAKE (1 << 16)
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/* PMSTS register defines */
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#define PMSTS_DISR (1 << 0)
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/* DCO register defines */
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#define DCO_DRPLOCK (1 << 0)
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#define DCO_CPGCLOCK (1 << 8)
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#define DCO_PMICTL (1 << 28)
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#define DCO_PMIDIS (1 << 29)
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#define DCO_IC (1 << 31)
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/* DECCCTRL register defines */
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#define DECCCTRL_SBEEN (1 << 0)
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#define DECCCTRL_DBEEN (1 << 1)
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#define DECCCTRL_ENCBGEN (1 << 17)
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/* DRAM init command */
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#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
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#define DCMD_REF(rnk) (1 | ((rnk) << 22))
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#define DCMD_PRE(rnk) (2 | ((rnk) << 22))
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#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6))
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#define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
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#define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
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#define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
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#define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
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#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6))
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#define DCMD_NOP(rnk) (7 | ((rnk) << 22))
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#define DDR3_EMRS1_DIC_40 0
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#define DDR3_EMRS1_DIC_34 1
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#define DDR3_EMRS1_RTTNOM_0 0
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#define DDR3_EMRS1_RTTNOM_60 0x04
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#define DDR3_EMRS1_RTTNOM_120 0x40
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#define DDR3_EMRS1_RTTNOM_40 0x44
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#define DDR3_EMRS1_RTTNOM_20 0x200
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#define DDR3_EMRS1_RTTNOM_30 0x204
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#define DDR3_EMRS2_RTTWR_60 (1 << 9)
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#define DDR3_EMRS2_RTTWR_120 (1 << 10)
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/* BEGIN DDRIO Registers */
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/* DDR IOs & COMPs */
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#define DDRIODQ_BL_OFFSET 0x0800
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#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
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#define DDRIOCCC_CH_OFFSET 0x0800
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#define DDRCOMP_CH_OFFSET 0x0100
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/* CH0-BL01-DQ */
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#define DQOBSCKEBBCTL 0x0000
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#define DQDLLTXCTL 0x0004
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#define DQDLLRXCTL 0x0008
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#define DQMDLLCTL 0x000c
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#define B0RXIOBUFCTL 0x0010
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#define B0VREFCTL 0x0014
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#define B0RXOFFSET1 0x0018
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#define B0RXOFFSET0 0x001c
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#define B1RXIOBUFCTL 0x0020
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#define B1VREFCTL 0x0024
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#define B1RXOFFSET1 0x0028
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#define B1RXOFFSET0 0x002c
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#define DQDFTCTL 0x0030
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#define DQTRAINSTS 0x0034
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#define B1DLLPICODER0 0x0038
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#define B0DLLPICODER0 0x003c
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#define B1DLLPICODER1 0x0040
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#define B0DLLPICODER1 0x0044
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#define B1DLLPICODER2 0x0048
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#define B0DLLPICODER2 0x004c
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#define B1DLLPICODER3 0x0050
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#define B0DLLPICODER3 0x0054
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#define B1RXDQSPICODE 0x0058
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#define B0RXDQSPICODE 0x005c
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#define B1RXDQPICODER32 0x0060
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#define B1RXDQPICODER10 0x0064
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#define B0RXDQPICODER32 0x0068
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#define B0RXDQPICODER10 0x006c
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#define B01PTRCTL0 0x0070
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#define B01PTRCTL1 0x0074
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#define B01DBCTL0 0x0078
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#define B01DBCTL1 0x007c
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#define B0LATCTL0 0x0080
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#define B1LATCTL0 0x0084
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#define B01LATCTL1 0x0088
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#define B0ONDURCTL 0x008c
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#define B1ONDURCTL 0x0090
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#define B0OVRCTL 0x0094
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#define B1OVRCTL 0x0098
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#define DQCTL 0x009c
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#define B0RK2RKCHGPTRCTRL 0x00a0
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#define B1RK2RKCHGPTRCTRL 0x00a4
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#define DQRK2RKCTL 0x00a8
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#define DQRK2RKPTRCTL 0x00ac
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#define B0RK2RKLAT 0x00b0
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#define B1RK2RKLAT 0x00b4
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#define DQCLKALIGNREG0 0x00b8
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#define DQCLKALIGNREG1 0x00bc
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#define DQCLKALIGNREG2 0x00c0
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#define DQCLKALIGNSTS0 0x00c4
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#define DQCLKALIGNSTS1 0x00c8
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#define DQCLKGATE 0x00cc
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#define B0COMPSLV1 0x00d0
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#define B1COMPSLV1 0x00d4
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#define B0COMPSLV2 0x00d8
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#define B1COMPSLV2 0x00dc
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#define B0COMPSLV3 0x00e0
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#define B1COMPSLV3 0x00e4
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#define DQVISALANECR0TOP 0x00e8
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#define DQVISALANECR1TOP 0x00ec
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#define DQVISACONTROLCRTOP 0x00f0
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#define DQVISALANECR0BL 0x00f4
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#define DQVISALANECR1BL 0x00f8
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#define DQVISACONTROLCRBL 0x00fc
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#define DQTIMINGCTRL 0x010c
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/* CH0-ECC */
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#define ECCDLLTXCTL 0x2004
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#define ECCDLLRXCTL 0x2008
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#define ECCMDLLCTL 0x200c
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#define ECCB1DLLPICODER0 0x2038
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#define ECCB1DLLPICODER1 0x2040
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#define ECCB1DLLPICODER2 0x2048
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#define ECCB1DLLPICODER3 0x2050
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#define ECCB01DBCTL0 0x2078
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#define ECCB01DBCTL1 0x207c
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#define ECCCLKALIGNREG0 0x20b8
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#define ECCCLKALIGNREG1 0x20bc
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#define ECCCLKALIGNREG2 0x20c0
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/* CH0-CMD */
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#define CMDOBSCKEBBCTL 0x4800
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#define CMDDLLTXCTL 0x4808
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#define CMDDLLRXCTL 0x480c
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#define CMDMDLLCTL 0x4810
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#define CMDRCOMPODT 0x4814
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#define CMDDLLPICODER0 0x4820
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#define CMDDLLPICODER1 0x4824
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#define CMDCFGREG0 0x4840
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#define CMDPTRREG 0x4844
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#define CMDCLKALIGNREG0 0x4850
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#define CMDCLKALIGNREG1 0x4854
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#define CMDCLKALIGNREG2 0x4858
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#define CMDPMCONFIG0 0x485c
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#define CMDPMDLYREG0 0x4860
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#define CMDPMDLYREG1 0x4864
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#define CMDPMDLYREG2 0x4868
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#define CMDPMDLYREG3 0x486c
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#define CMDPMDLYREG4 0x4870
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#define CMDCLKALIGNSTS0 0x4874
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#define CMDCLKALIGNSTS1 0x4878
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#define CMDPMSTS0 0x487c
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#define CMDPMSTS1 0x4880
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#define CMDCOMPSLV 0x4884
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#define CMDBONUS0 0x488c
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#define CMDBONUS1 0x4890
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#define CMDVISALANECR0 0x4894
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#define CMDVISALANECR1 0x4898
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#define CMDVISACONTROLCR 0x489c
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#define CMDCLKGATE 0x48a0
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#define CMDTIMINGCTRL 0x48a4
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/* CH0-CLK-CTL */
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#define CCOBSCKEBBCTL 0x5800
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#define CCRCOMPIO 0x5804
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#define CCDLLTXCTL 0x5808
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#define CCDLLRXCTL 0x580c
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#define CCMDLLCTL 0x5810
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#define CCRCOMPODT 0x5814
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#define CCDLLPICODER0 0x5820
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#define CCDLLPICODER1 0x5824
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#define CCDDR3RESETCTL 0x5830
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#define CCCFGREG0 0x5838
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#define CCCFGREG1 0x5840
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#define CCPTRREG 0x5844
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#define CCCLKALIGNREG0 0x5850
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#define CCCLKALIGNREG1 0x5854
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#define CCCLKALIGNREG2 0x5858
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#define CCPMCONFIG0 0x585c
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#define CCPMDLYREG0 0x5860
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#define CCPMDLYREG1 0x5864
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#define CCPMDLYREG2 0x5868
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#define CCPMDLYREG3 0x586c
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#define CCPMDLYREG4 0x5870
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#define CCCLKALIGNSTS0 0x5874
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#define CCCLKALIGNSTS1 0x5878
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#define CCPMSTS0 0x587c
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#define CCPMSTS1 0x5880
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#define CCCOMPSLV1 0x5884
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#define CCCOMPSLV2 0x5888
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#define CCCOMPSLV3 0x588c
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#define CCBONUS0 0x5894
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#define CCBONUS1 0x5898
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#define CCVISALANECR0 0x589c
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#define CCVISALANECR1 0x58a0
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#define CCVISACONTROLCR 0x58a4
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#define CCCLKGATE 0x58a8
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#define CCTIMINGCTL 0x58ac
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/* COMP */
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#define CMPCTRL 0x6800
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#define SOFTRSTCNTL 0x6804
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#define MSCNTR 0x6808
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#define NMSCNTRL 0x680c
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#define LATCH1CTL 0x6814
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#define COMPVISALANECR0 0x681c
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#define COMPVISALANECR1 0x6820
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#define COMPVISACONTROLCR 0x6824
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#define COMPBONUS0 0x6830
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#define TCOCNTCTRL 0x683c
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#define DQANAODTPUCTL 0x6840
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#define DQANAODTPDCTL 0x6844
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#define DQANADRVPUCTL 0x6848
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#define DQANADRVPDCTL 0x684c
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#define DQANADLYPUCTL 0x6850
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#define DQANADLYPDCTL 0x6854
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#define DQANATCOPUCTL 0x6858
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#define DQANATCOPDCTL 0x685c
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#define CMDANADRVPUCTL 0x6868
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#define CMDANADRVPDCTL 0x686c
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#define CMDANADLYPUCTL 0x6870
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#define CMDANADLYPDCTL 0x6874
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#define CLKANAODTPUCTL 0x6880
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#define CLKANAODTPDCTL 0x6884
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#define CLKANADRVPUCTL 0x6888
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#define CLKANADRVPDCTL 0x688c
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#define CLKANADLYPUCTL 0x6890
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#define CLKANADLYPDCTL 0x6894
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#define CLKANATCOPUCTL 0x6898
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#define CLKANATCOPDCTL 0x689c
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#define DQSANAODTPUCTL 0x68a0
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#define DQSANAODTPDCTL 0x68a4
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#define DQSANADRVPUCTL 0x68a8
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#define DQSANADRVPDCTL 0x68ac
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#define DQSANADLYPUCTL 0x68b0
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#define DQSANADLYPDCTL 0x68b4
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#define DQSANATCOPUCTL 0x68b8
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#define DQSANATCOPDCTL 0x68bc
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#define CTLANADRVPUCTL 0x68c8
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#define CTLANADRVPDCTL 0x68cc
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#define CTLANADLYPUCTL 0x68d0
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#define CTLANADLYPDCTL 0x68d4
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#define CHNLBUFSTATIC 0x68f0
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#define COMPOBSCNTRL 0x68f4
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#define COMPBUFFDBG0 0x68f8
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#define COMPBUFFDBG1 0x68fc
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#define CFGMISCCH0 0x6900
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#define COMPEN0CH0 0x6904
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#define COMPEN1CH0 0x6908
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#define COMPEN2CH0 0x690c
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#define STATLEGEN0CH0 0x6910
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#define STATLEGEN1CH0 0x6914
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#define DQVREFCH0 0x6918
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#define CMDVREFCH0 0x691c
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#define CLKVREFCH0 0x6920
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#define DQSVREFCH0 0x6924
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#define CTLVREFCH0 0x6928
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#define TCOVREFCH0 0x692c
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#define DLYSELCH0 0x6930
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#define TCODRAMBUFODTCH0 0x6934
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#define CCBUFODTCH0 0x6938
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#define RXOFFSETCH0 0x693c
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#define DQODTPUCTLCH0 0x6940
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#define DQODTPDCTLCH0 0x6944
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#define DQDRVPUCTLCH0 0x6948
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#define DQDRVPDCTLCH0 0x694c
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#define DQDLYPUCTLCH0 0x6950
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#define DQDLYPDCTLCH0 0x6954
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#define DQTCOPUCTLCH0 0x6958
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#define DQTCOPDCTLCH0 0x695c
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#define CMDDRVPUCTLCH0 0x6968
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#define CMDDRVPDCTLCH0 0x696c
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#define CMDDLYPUCTLCH0 0x6970
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#define CMDDLYPDCTLCH0 0x6974
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#define CLKODTPUCTLCH0 0x6980
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#define CLKODTPDCTLCH0 0x6984
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#define CLKDRVPUCTLCH0 0x6988
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#define CLKDRVPDCTLCH0 0x698c
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#define CLKDLYPUCTLCH0 0x6990
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#define CLKDLYPDCTLCH0 0x6994
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#define CLKTCOPUCTLCH0 0x6998
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#define CLKTCOPDCTLCH0 0x699c
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#define DQSODTPUCTLCH0 0x69a0
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#define DQSODTPDCTLCH0 0x69a4
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#define DQSDRVPUCTLCH0 0x69a8
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#define DQSDRVPDCTLCH0 0x69ac
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#define DQSDLYPUCTLCH0 0x69b0
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#define DQSDLYPDCTLCH0 0x69b4
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#define DQSTCOPUCTLCH0 0x69b8
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#define DQSTCOPDCTLCH0 0x69bc
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#define CTLDRVPUCTLCH0 0x69c8
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#define CTLDRVPDCTLCH0 0x69cc
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#define CTLDLYPUCTLCH0 0x69d0
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#define CTLDLYPDCTLCH0 0x69d4
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#define FNLUPDTCTLCH0 0x69f0
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/* PLL */
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#define MPLLCTRL0 0x7800
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#define MPLLCTRL1 0x7808
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#define MPLLCSR0 0x7810
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#define MPLLCSR1 0x7814
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#define MPLLCSR2 0x7820
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#define MPLLDFT 0x7828
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#define MPLLMON0CTL 0x7830
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#define MPLLMON1CTL 0x7838
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#define MPLLMON2CTL 0x783c
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#define SFRTRIM 0x7850
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#define MPLLDFTOUT0 0x7858
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#define MPLLDFTOUT1 0x785c
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#define MASTERRSTN 0x7880
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#define PLLLOCKDEL 0x7884
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#define SFRDEL 0x7888
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#define CRUVISALANECR0 0x78f0
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#define CRUVISALANECR1 0x78f4
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#define CRUVISACONTROLCR 0x78f8
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#define IOSFVISALANECR0 0x78fc
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#define IOSFVISALANECR1 0x7900
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#define IOSFVISACONTROLCR 0x7904
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/* END DDRIO Registers */
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/* DRAM Specific Message Bus OpCodes */
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#define MSG_OP_DRAM_INIT 0x68
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#define MSG_OP_DRAM_WAKE 0xca
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#define SAMPLE_SIZE 6
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/* must be less than this number to enable early deadband */
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#define EARLY_DB 0x12
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/* must be greater than this number to enable late deadband */
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#define LATE_DB 0x34
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#define CHX_REGS (11 * 4)
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#define FULL_CLK 128
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#define HALF_CLK 64
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#define QRTR_CLK 32
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#define MCEIL(num, den) ((uint8_t)((num + den - 1) / den))
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#define MMAX(a, b) ((a) > (b) ? (a) : (b))
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#define DEAD_LOOP() for (;;);
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#define MIN_RDQS_EYE 10 /* in PI Codes */
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#define MIN_VREF_EYE 10 /* in VREF Codes */
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/* how many RDQS codes to jump while margining */
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#define RDQS_STEP 1
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/* how many VREF codes to jump while margining */
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#define VREF_STEP 1
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/* offset into "vref_codes[]" for minimum allowed VREF setting */
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#define VREF_MIN 0x00
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/* offset into "vref_codes[]" for maximum allowed VREF setting */
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#define VREF_MAX 0x3f
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#define RDQS_MIN 0x00 /* minimum RDQS delay value */
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#define RDQS_MAX 0x3f /* maximum RDQS delay value */
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/* how many WDQ codes to jump while margining */
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#define WDQ_STEP 1
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enum {
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B, /* BOTTOM VREF */
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T /* TOP VREF */
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};
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enum {
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L, /* LEFT RDQS */
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R /* RIGHT RDQS */
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};
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/* Memory Options */
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/* enable STATIC timing settings for RCVN (BACKUP_MODE) */
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#undef BACKUP_RCVN
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/* enable STATIC timing settings for WDQS (BACKUP_MODE) */
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#undef BACKUP_WDQS
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/* enable STATIC timing settings for RDQS (BACKUP_MODE) */
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#undef BACKUP_RDQS
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/* enable STATIC timing settings for WDQ (BACKUP_MODE) */
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#undef BACKUP_WDQ
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/* enable *COMP overrides (BACKUP_MODE) */
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#undef BACKUP_COMPS
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/* enable the RD_TRAIN eye check */
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#undef RX_EYE_CHECK
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/* enable Host to Memory Clock Alignment */
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#define HMC_TEST
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/* enable multi-rank support via rank2rank sharing */
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#define R2R_SHARING
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/* disable signals not used in 16bit mode of DDRIO */
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#define FORCE_16BIT_DDRIO
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#define PLATFORM_ID 1
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void clear_self_refresh(struct mrc_params *mrc_params);
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void prog_ddr_timing_control(struct mrc_params *mrc_params);
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void prog_decode_before_jedec(struct mrc_params *mrc_params);
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void perform_ddr_reset(struct mrc_params *mrc_params);
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void ddrphy_init(struct mrc_params *mrc_params);
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void perform_jedec_init(struct mrc_params *mrc_params);
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void set_ddr_init_complete(struct mrc_params *mrc_params);
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void restore_timings(struct mrc_params *mrc_params);
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void default_timings(struct mrc_params *mrc_params);
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void rcvn_cal(struct mrc_params *mrc_params);
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void wr_level(struct mrc_params *mrc_params);
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void prog_page_ctrl(struct mrc_params *mrc_params);
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void rd_train(struct mrc_params *mrc_params);
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void wr_train(struct mrc_params *mrc_params);
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void store_timings(struct mrc_params *mrc_params);
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void enable_scrambling(struct mrc_params *mrc_params);
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void prog_ddr_control(struct mrc_params *mrc_params);
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void prog_dra_drb(struct mrc_params *mrc_params);
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void perform_wake(struct mrc_params *mrc_params);
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void change_refresh_period(struct mrc_params *mrc_params);
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void set_auto_refresh(struct mrc_params *mrc_params);
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void ecc_enable(struct mrc_params *mrc_params);
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void memory_test(struct mrc_params *mrc_params);
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void lock_registers(struct mrc_params *mrc_params);
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#endif /* _SMC_H_ */
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