upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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272 lines
8.9 KiB
272 lines
8.9 KiB
#ifndef __HW_S3C4510_H
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#define __HW_S3C4510_H
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/*
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* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
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* Curt Brune <curt@cucy.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description: Samsung S3C4510B register layout
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*/
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/*------------------------------------------------------------------------
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* ASIC Address Definition
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*----------------------------------------------------------------------*/
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/* L1 8KB on chip SRAM base address */
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#define SRAM_BASE (0x03fe0000)
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/* Special Register Start Address After System Reset */
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#define REG_BASE (0x03ff0000)
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#define SPSTR (REG_BASE)
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/* *********************** */
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/* System Manager Register */
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/* *********************** */
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#define REG_SYSCFG (REG_BASE+0x0000)
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#define REG_CLKCON (REG_BASE+0x3000)
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#define REG_EXTACON0 (REG_BASE+0x3008)
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#define REG_EXTACON1 (REG_BASE+0x300c)
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#define REG_EXTDBWTH (REG_BASE+0x3010)
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#define REG_ROMCON0 (REG_BASE+0x3014)
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#define REG_ROMCON1 (REG_BASE+0x3018)
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#define REG_ROMCON2 (REG_BASE+0x301c)
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#define REG_ROMCON3 (REG_BASE+0x3020)
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#define REG_ROMCON4 (REG_BASE+0x3024)
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#define REG_ROMCON5 (REG_BASE+0x3028)
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#define REG_DRAMCON0 (REG_BASE+0x302c)
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#define REG_DRAMCON1 (REG_BASE+0x3030)
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#define REG_DRAMCON2 (REG_BASE+0x3034)
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#define REG_DRAMCON3 (REG_BASE+0x3038)
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#define REG_REFEXTCON (REG_BASE+0x303c)
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/* *********************** */
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/* Ethernet BDMA Register */
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/* *********************** */
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#define REG_BDMATXCON (REG_BASE+0x9000)
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#define REG_BDMARXCON (REG_BASE+0x9004)
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#define REG_BDMATXPTR (REG_BASE+0x9008)
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#define REG_BDMARXPTR (REG_BASE+0x900c)
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#define REG_BDMARXLSZ (REG_BASE+0x9010)
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#define REG_BDMASTAT (REG_BASE+0x9014)
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/* Content Address Memory */
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#define REG_CAM_BASE (REG_BASE+0x9100)
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#define REG_BDMATXBUF (REG_BASE+0x9200)
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#define REG_BDMARXBUF (REG_BASE+0x9800)
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/* *********************** */
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/* Ethernet MAC Register */
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/* *********************** */
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#define REG_MACCON (REG_BASE+0xa000)
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#define REG_CAMCON (REG_BASE+0xa004)
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#define REG_MACTXCON (REG_BASE+0xa008)
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#define REG_MACTXSTAT (REG_BASE+0xa00c)
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#define REG_MACRXCON (REG_BASE+0xa010)
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#define REG_MACRXSTAT (REG_BASE+0xa014)
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#define REG_STADATA (REG_BASE+0xa018)
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#define REG_STACON (REG_BASE+0xa01c)
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#define REG_CAMEN (REG_BASE+0xa028)
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#define REG_EMISSCNT (REG_BASE+0xa03c)
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#define REG_EPZCNT (REG_BASE+0xa040)
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#define REG_ERMPZCNT (REG_BASE+0xa044)
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#define REG_ETXSTAT (REG_BASE+0x9040)
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#define REG_MACRXDESTR (REG_BASE+0xa064)
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#define REG_MACRXSTATEM (REG_BASE+0xa090)
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#define REG_MACRXFIFO (REG_BASE+0xa200)
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/********************/
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/* I2C Bus Register */
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/********************/
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#define REG_I2C_CON (REG_BASE+0xf000)
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#define REG_I2C_BUF (REG_BASE+0xf004)
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#define REG_I2C_PS (REG_BASE+0xf008)
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#define REG_I2C_COUNT (REG_BASE+0xf00c)
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/********************/
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/* GDMA 0 */
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/********************/
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#define REG_GDMACON0 (REG_BASE+0xb000)
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#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
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#define REG_GDMASRC0 (REG_BASE+0xb004)
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#define REG_GDMADST0 (REG_BASE+0xb008)
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#define REG_GDMACNT0 (REG_BASE+0xb00c)
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/********************/
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/* GDMA 1 */
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/********************/
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#define REG_GDMACON1 (REG_BASE+0xc000)
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#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
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#define REG_GDMASRC1 (REG_BASE+0xc004)
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#define REG_GDMADST1 (REG_BASE+0xc008)
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#define REG_GDMACNT1 (REG_BASE+0xc00c)
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/********************/
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/* UART 0 */
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/********************/
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#define UART0_BASE (REG_BASE+0xd000)
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#define REG_UART0_LCON (REG_BASE+0xd000)
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#define REG_UART0_CTRL (REG_BASE+0xd004)
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#define REG_UART0_STAT (REG_BASE+0xd008)
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#define REG_UART0_TXB (REG_BASE+0xd00c)
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#define REG_UART0_RXB (REG_BASE+0xd010)
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#define REG_UART0_BAUD_DIV (REG_BASE+0xd014)
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#define REG_UART0_BAUD_CNT (REG_BASE+0xd018)
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#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C)
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/********************/
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/* UART 1 */
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/********************/
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#define UART1_BASE (REG_BASE+0xe000)
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#define REG_UART1_LCON (REG_BASE+0xe000)
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#define REG_UART1_CTRL (REG_BASE+0xe004)
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#define REG_UART1_STAT (REG_BASE+0xe008)
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#define REG_UART1_TXB (REG_BASE+0xe00c)
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#define REG_UART1_RXB (REG_BASE+0xe010)
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#define REG_UART1_BAUD_DIV (REG_BASE+0xe014)
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#define REG_UART1_BAUD_CNT (REG_BASE+0xe018)
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#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C)
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/********************/
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/* Timer Register */
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/********************/
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#define REG_TMOD (REG_BASE+0x6000)
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#define REG_TDATA0 (REG_BASE+0x6004)
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#define REG_TDATA1 (REG_BASE+0x6008)
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#define REG_TCNT0 (REG_BASE+0x600c)
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#define REG_TCNT1 (REG_BASE+0x6010)
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/**********************/
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/* I/O Port Interface */
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/**********************/
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#define REG_IOPMODE (REG_BASE+0x5000)
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#define REG_IOPCON (REG_BASE+0x5004)
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#define REG_IOPDATA (REG_BASE+0x5008)
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/*********************************/
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/* Interrupt Controller Register */
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/*********************************/
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#define REG_INTMODE (REG_BASE+0x4000)
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#define REG_INTPEND (REG_BASE+0x4004)
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#define REG_INTMASK (REG_BASE+0x4008)
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#define REG_INTPRI0 (REG_BASE+0x400c)
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#define REG_INTPRI1 (REG_BASE+0x4010)
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#define REG_INTPRI2 (REG_BASE+0x4014)
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#define REG_INTPRI3 (REG_BASE+0x4018)
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#define REG_INTPRI4 (REG_BASE+0x401c)
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#define REG_INTPRI5 (REG_BASE+0x4020)
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#define REG_INTOFFSET (REG_BASE+0x4024)
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#define REG_INTPNDPRI (REG_BASE+0x4028)
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#define REG_INTPNDTST (REG_BASE+0x402C)
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/*********************************/
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/* CACHE CONTROL MASKS */
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/*********************************/
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#define CACHE_STALL (0x00000001)
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#define CACHE_ENABLE (0x00000002)
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#define CACHE_WRITE_BUFF (0x00000004)
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#define CACHE_MODE (0x00000030)
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#define CACHE_MODE_00 (0x00000000)
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#define CACHE_MODE_01 (0x00000010)
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#define CACHE_MODE_10 (0x00000020)
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/*********************************/
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/* CACHE RAM BASE ADDRESSES */
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/*********************************/
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#define CACHE_SET0_RAM (0x10000000)
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#define CACHE_SET1_RAM (0x10800000)
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#define CACHE_TAG_RAM (0x11000000)
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/*********************************/
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/* CACHE_DISABLE MASK */
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/*********************************/
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#define CACHE_DISABLE_MASK (0x04000000)
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#define GET_REG(reg) (*((volatile u32 *)(reg)))
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#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val)))
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#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask))
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#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
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#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val)))
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#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF)))
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#define GET__U8(reg) (*((volatile u8 *)(reg)))
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#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF))
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#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF)
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#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); }
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#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); }
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/***********************************/
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/* CLOCK CONSTANTS -- 50 MHz Clock */
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/***********************************/
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#define CLK_FREQ_MHZ (50)
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#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */
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#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */
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/*********************************************************/
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/* TIMER MODE REGISTER */
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/*********************************************************/
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#define TM0_RUN 0x01 /* Timer 0 enable */
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#define TM0_TOGGLE 0x02 /* 0, interval mode */
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#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
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#define TM1_RUN 0x08 /* Timer 1 enable */
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#define TM1_TOGGLE 0x10 /* 0, interval mode */
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#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
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/*********************************/
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/* INTERRUPT SOURCES */
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/*********************************/
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#define INT_EXTINT0 0
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#define INT_EXTINT1 1
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#define INT_EXTINT2 2
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#define INT_EXTINT3 3
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#define INT_UARTTX0 4
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#define INT_UARTRX0 5
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#define INT_UARTTX1 6
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#define INT_UARTRX1 7
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#define INT_GDMA0 8
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#define INT_GDMA1 9
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#define INT_TIMER0 10
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#define INT_TIMER1 11
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#define INT_HDLCTXA 12
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#define INT_HDLCRXA 13
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#define INT_HDLCTXB 14
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#define INT_HDLCRXB 15
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#define INT_BDMATX 16
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#define INT_BDMARX 17
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#define INT_MACTX 18
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#define INT_MACRX 19
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#define INT_IIC 20
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#define INT_GLOBAL 21
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#define N_IRQS (21)
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#ifndef __ASSEMBLER__
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struct _irq_handler {
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void *m_data;
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void (*m_func)( void *data);
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};
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#endif
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#endif /* __S3C4510_h */
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