upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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344 lines
8.4 KiB
344 lines
8.4 KiB
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#if 0
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#define FPGA_DEBUG
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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/*
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* include common auto-update code (for esd boards)
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*/
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#include "../common/auto_update.h"
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au_image_t au_image[] = {
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{"plu405/preinst.img", 0, -1, AU_SCRIPT},
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{"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
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{"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
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{"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
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{"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
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{"plu405/postinst.img", 0, 0, AU_SCRIPT},
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};
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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/* Prototypes */
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int gunzip(void *, int, unsigned char *, unsigned long *);
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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return 0;
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}
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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/*
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* Reset external DUARTs
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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udelay(10); /* wait 10us */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
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/*
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* Setup EEPROM write protection
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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out_8(duart0_mcr, 0x08);
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out_8(duart1_mcr, 0x08);
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming PLU405");
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} else {
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puts(str);
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}
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putc ('\n');
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return 0;
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}
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
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} else { /* release RESET */
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*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
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}
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}
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#endif /* CONFIG_IDE_RESET */
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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if (CFG_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int query = argc == 1;
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int state = 0;
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if (query) {
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/* Query write access state. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
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if (state < 0) {
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puts ("Query of write access state failed.\n");
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} else {
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printf ("Write access for device 0x%0x is %sabled.\n",
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
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state = 0;
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}
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} else {
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if ('0' == argv[1][0]) {
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/* Disable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
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} else {
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/* Enable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
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}
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if (state < 0) {
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puts ("Setup of write access state failed.\n");
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}
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}
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return state;
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}
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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"eepwren - Enable / disable / query EEPROM write access\n",
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NULL);
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#endif /* #if defined(CFG_EEPROM_WREN) */
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