upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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763 lines
29 KiB
763 lines
29 KiB
/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* FILENAME:
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*
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* xipif.h
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*
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* DESCRIPTION:
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*
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* The XIpIf component encapsulates the IPIF, which is the standard interface
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* that IP must adhere to when connecting to a bus. The purpose of this
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* component is to encapsulate the IPIF processing such that maintainability
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* is increased. This component does not provide a lot of abstraction from
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* from the details of the IPIF as it is considered a building block for
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* device drivers. A device driver designer must be familiar with the
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* details of the IPIF hardware to use this component.
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*
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* The IPIF hardware provides a building block for all hardware devices such
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* that each device does not need to reimplement these building blocks. The
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* IPIF contains other building blocks, such as FIFOs and DMA channels, which
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* are also common to many devices. These blocks are implemented as separate
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* hardware blocks and instantiated within the IPIF. The primary hardware of
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* the IPIF which is implemented by this software component is the interrupt
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* architecture. Since there are many blocks of a device which may generate
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* interrupts, all the interrupt processing is contained in the common part
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* of the device, the IPIF. This interrupt processing is for the device level
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* only and does not include any processing for the interrupt controller.
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*
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* A device is a mechanism such as an Ethernet MAC. The device is made
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* up of several parts which include an IPIF and the IP. The IPIF contains most
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* of the device infrastructure which is common to all devices, such as
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* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
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* be referred to as IPIF internal blocks since they are part of the IPIF and
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* are separate blocks that can be selected based upon the needs of the device.
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* The IP of the device is the logic that is unique to the device and interfaces
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* to the IPIF of the device.
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*
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* In general, there are two levels of registers within the IPIF. The first
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* level, referred to as the device level, contains registers which are for the
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* entire device. The second level, referred to as the IP level, contains
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* registers which are specific to the IP of the device. The two levels of
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* registers are designed to be hierarchical such that the device level is
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* is a more general register set above the more specific registers of the IP.
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* The IP level of registers provides functionality which is typically common
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* across all devices and allows IP designers to focus on the unique aspects
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* of the IP.
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*
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* Critical Sections
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*
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* It is the responsibility of the device driver designer to use critical
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* sections as necessary when calling functions of the IPIF. This component
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* does not use critical sections and it does access registers using
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* read-modify-write operations. Calls to IPIF functions from a main thread
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* and from an interrupt context could produce unpredictable behavior such that
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* the caller must provide the appropriate critical sections.
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*
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* Mutual Exclusion
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*
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* The functions of the IPIF are not thread safe such that the caller of all
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* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
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* exclusion across multiple IPIF components is not necessary.
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*
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* NOTES:
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*
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* None.
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*
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.23b jhl 02/27/01 Repartioned to minimize size
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*
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******************************************************************************/
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#ifndef XIPIF_H /* prevent circular inclusions */
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#define XIPIF_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include "xbasic_types.h"
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#include "xstatus.h"
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#include "xversion.h"
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/************************** Constant Definitions *****************************/
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/* the following constants define the register offsets for the registers of the
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* IPIF, there are some holes in the memory map for reserved addresses to allow
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* other registers to be added and still match the memory map of the interrupt
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* controller registers
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*/
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#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
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#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
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#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
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#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
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#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
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#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
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#define XIIF_V123B_RESET_MASK 0xAUL
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/* the following constant is used for the device global interrupt enable
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* register, to enable all interrupts for the device, this is the only bit
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* in the register
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*/
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#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL
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/* the following constants contain the masks to identify each internal IPIF
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* condition in the device registers of the IPIF, interrupts are assigned
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* in the register from LSB to the MSB
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*/
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#define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */
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/* The following constants contain interrupt IDs which identify each internal
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* IPIF condition, this value must correlate with the mask constant for the
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* error
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*/
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#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */
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#define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_RESET
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*
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* DESCRIPTION:
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*
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* Reset the IPIF component and hardware. This is a destructive operation that
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* could cause the loss of data since resetting the IPIF of a device also
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* resets the device using the IPIF and any blocks, such as FIFOs or DMA
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* channels, within the IPIF. All registers of the IPIF will contain their
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* reset value when this function returns.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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/* the following constant is used in the reset register to cause the IPIF to
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* reset
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*/
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#define XIIF_V123B_RESET(RegBaseAddress) \
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XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_WRITE_DISR
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*
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* DESCRIPTION:
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*
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* This function sets the device interrupt status register to the value.
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* This register indicates the status of interrupt sources for a device
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* which contains the IPIF. The status is independent of whether interrupts
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* are enabled and could be used for polling a device at a higher level rather
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* than a more detailed level.
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*
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* Each bit of the register correlates to a specific interrupt source within the
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* device which contains the IPIF. With the exception of some internal IPIF
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* conditions, the contents of this register are not latched but indicate
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* the live status of the interrupt sources within the device. Writing any of
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* the non-latched bits of the register will have no effect on the register.
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*
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* For the latched bits of this register only, setting a bit which is zero
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* within this register causes an interrupt to generated. The device global
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* interrupt enable register and the device interrupt enable register must be set
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* appropriately to allow an interrupt to be passed out of the device. The
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* interrupt is cleared by writing to this register with the bits to be
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* cleared set to a one and all others to zero. This register implements a
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* toggle on write functionality meaning any bits which are set in the value
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* written cause the bits in the register to change to the opposite state.
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*
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* This function writes the specified value to the register such that
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* some bits may be set and others cleared. It is the caller's responsibility
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* to get the value of the register prior to setting the value to prevent a
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* destructive behavior.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* Status contains the value to be written to the interrupt status register of
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* the device. The only bits which can be written are the latched bits which
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* contain the internal IPIF conditions. The following values may be used to
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* set the status register or clear an interrupt condition.
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*
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* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
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XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_READ_DISR
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*
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* DESCRIPTION:
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*
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* This function gets the device interrupt status register contents.
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* This register indicates the status of interrupt sources for a device
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* which contains the IPIF. The status is independent of whether interrupts
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* are enabled and could be used for polling a device at a higher level.
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*
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* Each bit of the register correlates to a specific interrupt source within the
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* device which contains the IPIF. With the exception of some internal IPIF
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* conditions, the contents of this register are not latched but indicate
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* the live status of the interrupt sources within the device.
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*
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* For only the latched bits of this register, the interrupt may be cleared by
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* writing to these bits in the status register.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* RETURN VALUE:
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*
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* A status which contains the value read from the interrupt status register of
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* the device. The bit definitions are specific to the device with
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* the exception of the latched internal IPIF condition bits. The following
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* values may be used to detect internal IPIF conditions in the status.
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*
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* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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#define XIIF_V123B_READ_DISR(RegBaseAddress) \
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XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_WRITE_DIER
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*
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* DESCRIPTION:
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*
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* This function sets the device interrupt enable register contents.
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* This register controls which interrupt sources of the device are allowed to
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* generate an interrupt. The device global interrupt enable register must also
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* be set appropriately for an interrupt to be passed out of the device.
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*
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* Each bit of the register correlates to a specific interrupt source within the
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* device which contains the IPIF. Setting a bit in this register enables that
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* interrupt source to generate an interrupt. Clearing a bit in this register
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* disables interrupt generation for that interrupt source.
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*
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* This function writes only the specified value to the register such that
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* some interrupts source may be enabled and others disabled. It is the
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* caller's responsibility to get the value of the interrupt enable register
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* prior to setting the value to prevent an destructive behavior.
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*
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* An interrupt source may not be enabled to generate an interrupt, but can
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* still be polled in the interrupt status register.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* Enable contains the value to be written to the interrupt enable register
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* of the device. The bit definitions are specific to the device with
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* the exception of the internal IPIF conditions. The following
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* values may be used to enable the internal IPIF conditions interrupts.
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*
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* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
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*
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* RETURN VALUE:
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*
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* None.
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*
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* NOTES:
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*
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* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
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* u32 Enable)
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*
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******************************************************************************/
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#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
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XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_READ_DIER
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*
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* DESCRIPTION:
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*
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* This function gets the device interrupt enable register contents.
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* This register controls which interrupt sources of the device
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* are allowed to generate an interrupt. The device global interrupt enable
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* register and the device interrupt enable register must also be set
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* appropriately for an interrupt to be passed out of the device.
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*
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* Each bit of the register correlates to a specific interrupt source within the
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* device which contains the IPIF. Setting a bit in this register enables that
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* interrupt source to generate an interrupt if the global enable is set
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* appropriately. Clearing a bit in this register disables interrupt generation
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* for that interrupt source regardless of the global interrupt enable.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* RETURN VALUE:
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*
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* The value read from the interrupt enable register of the device. The bit
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* definitions are specific to the device with the exception of the internal
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* IPIF conditions. The following values may be used to determine from the
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* value if the internal IPIF conditions interrupts are enabled.
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*
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* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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#define XIIF_V123B_READ_DIER(RegBaseAddress) \
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XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_READ_DIPR
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*
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* DESCRIPTION:
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*
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* This function gets the device interrupt pending register contents.
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* This register indicates the pending interrupt sources, those that are waiting
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* to be serviced by the software, for a device which contains the IPIF.
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* An interrupt must be enabled in the interrupt enable register of the IPIF to
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* be pending.
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*
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* Each bit of the register correlates to a specific interrupt source within the
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* the device which contains the IPIF. With the exception of some internal IPIF
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* conditions, the contents of this register are not latched since the condition
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* is latched in the IP interrupt status register, by an internal block of the
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* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register
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* is read only and is not latched, but it is necessary to acknowledge (clear)
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* the interrupt condition by performing the appropriate processing for the IP
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* or block within the IPIF.
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*
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* This register can be thought of as the contents of the interrupt status
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* register ANDed with the contents of the interrupt enable register.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* RETURN VALUE:
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*
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* The value read from the interrupt pending register of the device. The bit
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* definitions are specific to the device with the exception of the latched
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* internal IPIF condition bits. The following values may be used to detect
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* internal IPIF conditions in the value.
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*
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* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
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XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
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/******************************************************************************
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*
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* MACRO:
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*
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* XIIF_V123B_READ_DIIR
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*
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* DESCRIPTION:
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*
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* This function gets the device interrupt ID for the highest priority interrupt
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* which is pending from the interrupt ID register. This function provides
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* priority resolution such that faster interrupt processing is possible.
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* Without priority resolution, it is necessary for the software to read the
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* interrupt pending register and then check each interrupt source to determine
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* if an interrupt is pending. Priority resolution becomes more important as the
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* number of interrupt sources becomes larger.
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*
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* Interrupt priorities are based upon the bit position of the interrupt in the
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* interrupt pending register with bit 0 being the highest priority. The
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* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
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* highest priority. The interrupt ID register is live rather than latched such
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* that multiple calls to this function may not yield the same results. A
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* special value, outside of the interrupt priority range of 0 - 31, is
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* contained in the register which indicates that no interrupt is pending. This
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* may be useful for allowing software to continue processing interrupts in a
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* loop until there are no longer any interrupts pending.
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*
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* The interrupt ID is designed to allow a function pointer table to be used
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* in the software such that the interrupt ID is used as an index into that
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* table. The function pointer table could contain an instance pointer, such
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* as to DMA channel, and a function pointer to the function which handles
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* that interrupt. This design requires the interrupt processing of the device
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* driver to be partitioned into smaller more granular pieces based upon
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* hardware used by the device, such as DMA channels and FIFOs.
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*
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* It is not mandatory that this function be used by the device driver software.
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* It may choose to read the pending register and resolve the pending interrupt
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* priorities on it's own.
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*
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* ARGUMENTS:
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*
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* RegBaseAddress contains the base address of the IPIF registers.
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*
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* RETURN VALUE:
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*
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* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
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* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is
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* no interrupt pending. The following values may be used to identify the
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* interrupt ID for the internal IPIF interrupts.
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|
*
|
|
* XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
|
|
XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_GLOBAL_INTR_DISABLE
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function disables all interrupts for the device by writing to the global
|
|
* interrupt enable register. This register provides the ability to disable
|
|
* interrupts without any modifications to the interrupt enable register such
|
|
* that it is minimal effort to restore the interrupts to the previous enabled
|
|
* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to
|
|
* restore the interrupts to the previous enabled state. This function is
|
|
* designed to be used in critical sections of device drivers such that it is
|
|
* not necessary to disable other device interrupts.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
|
|
XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_GINTR_ENABLE
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function writes to the global interrupt enable register to enable
|
|
* interrupts from the device. This register provides the ability to enable
|
|
* interrupts without any modifications to the interrupt enable register such
|
|
* that it is minimal effort to restore the interrupts to the previous enabled
|
|
* state. This function does not enable individual interrupts as the interrupt
|
|
* enable register must be set appropriately. This function is designed to be
|
|
* used in critical sections of device drivers such that it is not necessary to
|
|
* disable other device interrupts.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \
|
|
XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
|
|
XIIF_V123B_GINTR_ENABLE_MASK)
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_IS_GINTR_ENABLED
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function determines if interrupts are enabled at the global level by
|
|
* reading the gloabl interrupt register. This register provides the ability to
|
|
* disable interrupts without any modifications to the interrupt enable register
|
|
* such that it is minimal effort to restore the interrupts to the previous
|
|
* enabled state.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* TRUE if interrupts are enabled for the IPIF, FALSE otherwise.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \
|
|
(XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \
|
|
XIIF_V123B_GINTR_ENABLE_MASK)
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_WRITE_IISR
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function sets the IP interrupt status register to the specified value.
|
|
* This register indicates the status of interrupt sources for the IP of the
|
|
* device. The IP is defined as the part of the device that connects to the
|
|
* IPIF. The status is independent of whether interrupts are enabled such that
|
|
* the status register may also be polled when interrupts are not enabled.
|
|
*
|
|
* Each bit of the register correlates to a specific interrupt source within the
|
|
* IP. All bits of this register are latched. Setting a bit which is zero
|
|
* within this register causes an interrupt to be generated. The device global
|
|
* interrupt enable register and the device interrupt enable register must be set
|
|
* appropriately to allow an interrupt to be passed out of the device. The
|
|
* interrupt is cleared by writing to this register with the bits to be
|
|
* cleared set to a one and all others to zero. This register implements a
|
|
* toggle on write functionality meaning any bits which are set in the value
|
|
* written cause the bits in the register to change to the opposite state.
|
|
*
|
|
* This function writes only the specified value to the register such that
|
|
* some status bits may be set and others cleared. It is the caller's
|
|
* responsibility to get the value of the register prior to setting the value
|
|
* to prevent an destructive behavior.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* Status contains the value to be written to the IP interrupt status
|
|
* register. The bit definitions are specific to the device IP.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
|
|
XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_READ_IISR
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function gets the contents of the IP interrupt status register.
|
|
* This register indicates the status of interrupt sources for the IP of the
|
|
* device. The IP is defined as the part of the device that connects to the
|
|
* IPIF. The status is independent of whether interrupts are enabled such
|
|
* that the status register may also be polled when interrupts are not enabled.
|
|
*
|
|
* Each bit of the register correlates to a specific interrupt source within the
|
|
* device. All bits of this register are latched. Writing a 1 to a bit within
|
|
* this register causes an interrupt to be generated if enabled in the interrupt
|
|
* enable register and the global interrupt enable is set. Since the status is
|
|
* latched, each status bit must be acknowledged in order for the bit in the
|
|
* status register to be updated. Each bit can be acknowledged by writing a
|
|
* 0 to the bit in the status register.
|
|
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* A status which contains the value read from the IP interrupt status register.
|
|
* The bit definitions are specific to the device IP.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_READ_IISR(RegBaseAddress) \
|
|
XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_WRITE_IIER
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
* This function sets the IP interrupt enable register contents. This register
|
|
* controls which interrupt sources of the IP are allowed to generate an
|
|
* interrupt. The global interrupt enable register and the device interrupt
|
|
* enable register must also be set appropriately for an interrupt to be
|
|
* passed out of the device containing the IPIF and the IP.
|
|
*
|
|
* Each bit of the register correlates to a specific interrupt source within the
|
|
* IP. Setting a bit in this register enables the interrupt source to generate
|
|
* an interrupt. Clearing a bit in this register disables interrupt generation
|
|
* for that interrupt source.
|
|
*
|
|
* This function writes only the specified value to the register such that
|
|
* some interrupt sources may be enabled and others disabled. It is the
|
|
* caller's responsibility to get the value of the interrupt enable register
|
|
* prior to setting the value to prevent an destructive behavior.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* Enable contains the value to be written to the IP interrupt enable register.
|
|
* The bit definitions are specific to the device IP.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* None.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* None.
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
|
|
XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
|
|
|
|
/******************************************************************************
|
|
*
|
|
* MACRO:
|
|
*
|
|
* XIIF_V123B_READ_IIER
|
|
*
|
|
* DESCRIPTION:
|
|
*
|
|
*
|
|
* This function gets the IP interrupt enable register contents. This register
|
|
* controls which interrupt sources of the IP are allowed to generate an
|
|
* interrupt. The global interrupt enable register and the device interrupt
|
|
* enable register must also be set appropriately for an interrupt to be
|
|
* passed out of the device containing the IPIF and the IP.
|
|
*
|
|
* Each bit of the register correlates to a specific interrupt source within the
|
|
* IP. Setting a bit in this register enables the interrupt source to generate
|
|
* an interrupt. Clearing a bit in this register disables interrupt generation
|
|
* for that interrupt source.
|
|
*
|
|
* ARGUMENTS:
|
|
*
|
|
* RegBaseAddress contains the base address of the IPIF registers.
|
|
*
|
|
* RETURN VALUE:
|
|
*
|
|
* The contents read from the IP interrupt enable register. The bit definitions
|
|
* are specific to the device IP.
|
|
*
|
|
* NOTES:
|
|
*
|
|
* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
|
|
*
|
|
******************************************************************************/
|
|
#define XIIF_V123B_READ_IIER(RegBaseAddress) \
|
|
XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
/*
|
|
* Initialization Functions
|
|
*/
|
|
XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
|
|
|
|
#endif /* end of protection macro */
|
|
|