upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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62 lines
1.4 KiB
62 lines
1.4 KiB
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/* Cache test
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*
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* This test verifies the CPU data and instruction cache using
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* several test scenarios.
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*/
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#include <post.h>
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#include <watchdog.h>
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#if CONFIG_POST & CONFIG_SYS_POST_CACHE
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#define CACHE_POST_SIZE 1024
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extern int cache_post_test1 (char *, unsigned int);
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extern int cache_post_test2 (char *, unsigned int);
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extern int cache_post_test3 (char *, unsigned int);
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extern int cache_post_test4 (char *, unsigned int);
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extern int cache_post_test5 (void);
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extern int cache_post_test6 (void);
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int cache_post_test (int flags)
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{
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int ints = disable_interrupts ();
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int res = 0;
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static char ta[CACHE_POST_SIZE + 0xf];
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char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test1 (testarea, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test2 (testarea, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test3 (testarea, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test4 (testarea, CACHE_POST_SIZE);
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test5 ();
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WATCHDOG_RESET ();
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if (res == 0)
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res = cache_post_test6 ();
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WATCHDOG_RESET ();
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if (ints)
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enable_interrupts ();
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return res;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
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