upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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179 lines
4.1 KiB
179 lines
4.1 KiB
#define ASSEMBLY
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#include <linux/config.h>
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#include <config.h>
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#include <asm/blackfin.h>
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#include <asm/mem_init.h>
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.global init_sdram;
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#if (CONFIG_CCLK_DIV == 1)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
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#endif
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#if (CONFIG_CCLK_DIV == 2)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
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#endif
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#if (CONFIG_CCLK_DIV == 4)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
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#endif
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#if (CONFIG_CCLK_DIV == 8)
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#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
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#endif
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#ifndef CONFIG_CCLK_ACT_DIV
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#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
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#endif
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init_sdram:
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[--SP] = ASTAT;
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[--SP] = RETS;
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[--SP] = (R7:0);
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[--SP] = (P5:0);
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#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
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p0.h = hi(SPI_BAUD);
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p0.l = lo(SPI_BAUD);
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r0.l = CONFIG_SPI_BAUD;
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w[p0] = r0.l;
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SSYNC;
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#endif
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/*
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* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
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*/
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p0.h = hi(PLL_LOCKCNT);
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p0.l = lo(PLL_LOCKCNT);
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r0 = 0x300(Z);
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w[p0] = r0.l;
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ssync;
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/*
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* Put SDRAM in self-refresh, incase anything is running
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*/
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITSET (R0, 24);
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[P2] = R0;
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SSYNC;
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/*
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* Set PLL_CTL with the value that we calculate in R0
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* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
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* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
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* - [7] = output delay (add 200ps of delay to mem signals)
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* - [6] = input delay (add 200ps of input delay to mem signals)
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* - [5] = PDWN : 1=All Clocks off
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* - [3] = STOPCK : 1=Core Clock off
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* - [1] = PLL_OFF : 1=Disable Power to PLL
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* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
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* all other bits set to zero
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*/
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r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
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r0 = r0 << 9; /* Shift it over, */
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r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
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r0 = r1 | r0;
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r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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cli r2; /* Disable interrupts */
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ssync;
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w[p0] = r0.l; /* Set the value */
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idle; /* Wait for the PLL to stablize */
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sti r2; /* Enable interrupts */
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check_again:
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p0.h = hi(PLL_STAT);
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p0.l = lo(PLL_STAT);
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R0 = W[P0](Z);
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CC = BITTST(R0,5);
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if ! CC jump check_again;
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/* Configure SCLK & CCLK Dividers */
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r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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p0.h = hi(PLL_DIV);
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p0.l = lo(PLL_DIV);
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w[p0] = r0.l;
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ssync;
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/*
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* We now are running at speed, time to set the Async mem bank wait states
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* This will speed up execution, since we are normally running from FLASH.
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*/
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p2.h = (EBIU_AMBCTL1 >> 16);
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p2.l = (EBIU_AMBCTL1 & 0xFFFF);
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r0.h = (AMBCTL1VAL >> 16);
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r0.l = (AMBCTL1VAL & 0xFFFF);
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[p2] = r0;
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ssync;
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p2.h = (EBIU_AMBCTL0 >> 16);
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p2.l = (EBIU_AMBCTL0 & 0xFFFF);
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r0.h = (AMBCTL0VAL >> 16);
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r0.l = (AMBCTL0VAL & 0xFFFF);
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[p2] = r0;
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ssync;
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p2.h = (EBIU_AMGCTL >> 16);
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p2.l = (EBIU_AMGCTL & 0xffff);
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r0 = AMGCTLVAL;
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w[p2] = r0;
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ssync;
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/*
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* Now, Initialize the SDRAM,
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* start with the SDRAM Refresh Rate Control Register
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*/
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p0.l = lo(EBIU_SDRRC);
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p0.h = hi(EBIU_SDRRC);
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r0 = mem_SDRRC;
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w[p0] = r0.l;
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ssync;
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/*
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* SDRAM Memory Bank Control Register - bank specific parameters
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*/
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p0.l = (EBIU_SDBCTL & 0xFFFF);
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p0.h = (EBIU_SDBCTL >> 16);
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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/*
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* SDRAM Global Control Register - global programmable parameters
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* Disable self-refresh
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*/
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITCLR (R0, 24);
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/*
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* Check if SDRAM is already powered up, if it is, enable self-refresh
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*/
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p0.h = hi(EBIU_SDSTAT);
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p0.l = lo(EBIU_SDSTAT);
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r2.l = w[p0];
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cc = bittst(r2,3);
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if !cc jump skip;
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NOP;
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BITSET (R0, 23);
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skip:
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[P2] = R0;
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SSYNC;
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/* Write in the new value in the register */
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R0.L = lo(mem_SDGCTL);
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R0.H = hi(mem_SDGCTL);
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[P2] = R0;
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SSYNC;
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nop;
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(P5:0) = [SP++];
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(R7:0) = [SP++];
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RETS = [SP++];
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ASTAT = [SP++];
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RTS;
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