upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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289 lines
15 KiB
289 lines
15 KiB
/*
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* (C) Copyright 2010
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Balaji Krishnamoorthy <balajitk@ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PANDA_MUX_DATA_H_
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#define _PANDA_MUX_DATA_H_
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#include <asm/arch/mux_omap4.h>
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const struct pad_conf_entry core_padconf_array_essential[] = {
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{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
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{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
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{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
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{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
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{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
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{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
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{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
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{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
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{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
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{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
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{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
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{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
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{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
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{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
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{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
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{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
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{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
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{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
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{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
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{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
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{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
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{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
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{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
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{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
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{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
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{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
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{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
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{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
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{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
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{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
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{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
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{UART3_TX_IRTX, (M0)} /* uart3_tx */
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};
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const struct pad_conf_entry wkup_padconf_array_essential[] = {
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{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
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{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
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{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
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};
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const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
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{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
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};
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const struct pad_conf_entry core_padconf_array_non_essential[] = {
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{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
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{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
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{GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */
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{GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */
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{GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */
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{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */
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{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */
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{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */
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{GPMC_A16, (M3)}, /* gpio_40 */
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{GPMC_A17, (PTD | M3)}, /* gpio_41 */
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{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */
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{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */
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{GPMC_A20, (IEN | M3)}, /* gpio_44 */
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{GPMC_A21, (M3)}, /* gpio_45 */
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{GPMC_A22, (M3)}, /* gpio_46 */
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{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */
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{GPMC_A24, (PTD | M3)}, /* gpio_48 */
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{GPMC_A25, (PTD | M3)}, /* gpio_49 */
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{GPMC_NCS0, (M3)}, /* gpio_50 */
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{GPMC_NCS1, (IEN | M3)}, /* gpio_51 */
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{GPMC_NCS2, (IEN | M3)}, /* gpio_52 */
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{GPMC_NCS3, (IEN | M3)}, /* gpio_53 */
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{GPMC_NWP, (M3)}, /* gpio_54 */
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{GPMC_CLK, (PTD | M3)}, /* gpio_55 */
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{GPMC_NADV_ALE, (M3)}, /* gpio_56 */
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{GPMC_NBE0_CLE, (M3)}, /* gpio_59 */
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{GPMC_NBE1, (PTD | M3)}, /* gpio_60 */
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{GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */
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{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
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{C2C_DATA11, (PTD | M3)}, /* gpio_100 */
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{C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */
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{C2C_DATA13, (PTD | M3)}, /* gpio_102 */
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{C2C_DATA14, (M1)}, /* dsi2_te0 */
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{C2C_DATA15, (PTD | M3)}, /* gpio_104 */
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{HDMI_HPD, (M0)}, /* hdmi_hpd */
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{HDMI_CEC, (M0)}, /* hdmi_cec */
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{HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
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{HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
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{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
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{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
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{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
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{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
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{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
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{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
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{CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
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{CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
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{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
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{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
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{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
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{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
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{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
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{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
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{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
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{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
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{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
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{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
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{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
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{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
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{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
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{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
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{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
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{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
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{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
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{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
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{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
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{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
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{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
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{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
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{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
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{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
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{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
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{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
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{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
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{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
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{ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */
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{ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */
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{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */
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{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */
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{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
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{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
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{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
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{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
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{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
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{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
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{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
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{ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */
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{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
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{UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */
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{UART2_RTS, (M7)}, /* uart2_rts */
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{UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */
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{UART2_TX, (M7)}, /* uart2_tx */
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{HDQ_SIO, (M3)}, /* gpio_127 */
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{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
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{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
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{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
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{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
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{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */
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{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */
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{MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */
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{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
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{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
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{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
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{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
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{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
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{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
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{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
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{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
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{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
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{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
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{UART4_RX, (IEN | M0)}, /* uart4_rx */
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{UART4_TX, (M0)}, /* uart4_tx */
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{USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */
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{USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
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{USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
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{USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
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{USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
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{USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
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{USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
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{USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
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{USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
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{USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
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{USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
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{USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
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{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */
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{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */
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{UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */
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{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
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{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
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{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
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{UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */
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{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
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{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
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{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
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{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
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{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
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{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
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{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
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{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
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{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
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{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
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{FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
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{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
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{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
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{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
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{SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
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{SYS_BOOT1, (M3)}, /* gpio_185 */
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{SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
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{SYS_BOOT3, (M3)}, /* gpio_187 */
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{SYS_BOOT4, (M3)}, /* gpio_188 */
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{SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
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{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
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{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
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{DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */
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{DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */
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{DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */
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{DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */
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{DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */
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{DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */
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{DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */
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{DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */
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{DPM_EMU10, (IEN | M5)}, /* dispc2_de */
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{DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */
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{DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */
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{DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */
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{DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */
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{DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */
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{DPM_EMU16, (M3)}, /* gpio_27 */
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{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
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{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
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{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
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};
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const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
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{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
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};
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const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
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{ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
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};
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const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
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{PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
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{PAD1_SIM_CLK, (M0)}, /* sim_clk */
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{PAD0_SIM_RESET, (M0)}, /* sim_reset */
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{PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
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{PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
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{PAD1_FREF_XTAL_IN, (M0)}, /* # */
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{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
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{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
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{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
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{PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
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{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
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{PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */
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{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
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{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
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{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
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{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
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{PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
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{PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
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};
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const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
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{PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */
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};
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#endif /* _PANDA_MUX_DATA_H_ */
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