upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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86 lines
1.7 KiB
86 lines
1.7 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard (void)
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{
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puts ("Board: Freescale M5282EVB Evaluation Board\n");
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return 0;
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}
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int dram_init(void)
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{
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u32 dramsize, i, dramclk;
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
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{
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dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
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/* Initialize DRAM Control Register: DCR */
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MCFSDRAMC_DCR = (0
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| MCFSDRAMC_DCR_RTIM_6
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| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
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asm("nop");
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/* Initialize DACR0 */
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MCFSDRAMC_DACR0 = (0
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| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
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| MCFSDRAMC_DACR_CASL(1)
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| MCFSDRAMC_DACR_CBM(3)
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| MCFSDRAMC_DACR_PS_32);
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asm("nop");
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/* Initialize DMR0 */
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MCFSDRAMC_DMR0 = (0
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| ((dramsize - 1) & 0xFFFC0000)
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| MCFSDRAMC_DMR_V);
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asm("nop");
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/* Set IP (bit 3) in DACR */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
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asm("nop");
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/* Wait 30ns to allow banks to precharge */
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for (i = 0; i < 5; i++) {
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asm ("nop");
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}
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/* Write to this block to initiate precharge */
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*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
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asm("nop");
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/* Set RE (bit 15) in DACR */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
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asm("nop");
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/* Wait for at least 8 auto refresh cycles to occur */
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for (i = 0; i < 2000; i++) {
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asm(" nop");
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}
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/* Finish the configuration by issuing the IMRS. */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
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asm("nop");
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/* Write to the SDRAM Mode Register */
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*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
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}
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gd->ram_size = dramsize;
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return 0;
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}
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