upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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169 lines
5.2 KiB
169 lines
5.2 KiB
/*
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* SSI Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __SSI_H__
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#define __SSI_H__
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typedef struct ssi {
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u32 tx0;
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u32 tx1;
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u32 rx0;
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u32 rx1;
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u32 cr;
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u32 isr;
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u32 ier;
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u32 tcr;
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u32 rcr;
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u32 ccr;
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u8 resv0[0x4];
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u32 fcsr;
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u8 resv1[0x8];
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u32 acr;
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u32 acadd;
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u32 acdat;
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u32 atag;
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u32 tmask;
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u32 rmask;
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} ssi_t;
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#define SSI_CR_CIS (0x00000200)
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#define SSI_CR_TCH (0x00000100)
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#define SSI_CR_MCE (0x00000080)
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#define SSI_CR_I2S_MASK (0xFFFFFF9F)
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#define SSI_CR_I2S_SLAVE (0x00000040)
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#define SSI_CR_I2S_MASTER (0x00000020)
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#define SSI_CR_I2S_NORMAL (0x00000000)
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#define SSI_CR_SYN (0x00000010)
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#define SSI_CR_NET (0x00000008)
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#define SSI_CR_RE (0x00000004)
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#define SSI_CR_TE (0x00000002)
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#define SSI_CR_SSI_EN (0x00000001)
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#define SSI_ISR_CMDAU (0x00040000)
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#define SSI_ISR_CMDDU (0x00020000)
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#define SSI_ISR_RXT (0x00010000)
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#define SSI_ISR_RDR1 (0x00008000)
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#define SSI_ISR_RDR0 (0x00004000)
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#define SSI_ISR_TDE1 (0x00002000)
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#define SSI_ISR_TDE0 (0x00001000)
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#define SSI_ISR_ROE1 (0x00000800)
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#define SSI_ISR_ROE0 (0x00000400)
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#define SSI_ISR_TUE1 (0x00000200)
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#define SSI_ISR_TUE0 (0x00000100)
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#define SSI_ISR_TFS (0x00000080)
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#define SSI_ISR_RFS (0x00000040)
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#define SSI_ISR_TLS (0x00000020)
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#define SSI_ISR_RLS (0x00000010)
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#define SSI_ISR_RFF1 (0x00000008)
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#define SSI_ISR_RFF0 (0x00000004)
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#define SSI_ISR_TFE1 (0x00000002)
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#define SSI_ISR_TFE0 (0x00000001)
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#define SSI_IER_RDMAE (0x00400000)
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#define SSI_IER_RIE (0x00200000)
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#define SSI_IER_TDMAE (0x00100000)
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#define SSI_IER_TIE (0x00080000)
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#define SSI_IER_CMDAU (0x00040000)
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#define SSI_IER_CMDU (0x00020000)
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#define SSI_IER_RXT (0x00010000)
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#define SSI_IER_RDR1 (0x00008000)
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#define SSI_IER_RDR0 (0x00004000)
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#define SSI_IER_TDE1 (0x00002000)
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#define SSI_IER_TDE0 (0x00001000)
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#define SSI_IER_ROE1 (0x00000800)
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#define SSI_IER_ROE0 (0x00000400)
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#define SSI_IER_TUE1 (0x00000200)
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#define SSI_IER_TUE0 (0x00000100)
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#define SSI_IER_TFS (0x00000080)
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#define SSI_IER_RFS (0x00000040)
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#define SSI_IER_TLS (0x00000020)
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#define SSI_IER_RLS (0x00000010)
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#define SSI_IER_RFF1 (0x00000008)
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#define SSI_IER_RFF0 (0x00000004)
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#define SSI_IER_TFE1 (0x00000002)
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#define SSI_IER_TFE0 (0x00000001)
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#define SSI_TCR_TXBIT0 (0x00000200)
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#define SSI_TCR_TFEN1 (0x00000100)
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#define SSI_TCR_TFEN0 (0x00000080)
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#define SSI_TCR_TFDIR (0x00000040)
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#define SSI_TCR_TXDIR (0x00000020)
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#define SSI_TCR_TSHFD (0x00000010)
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#define SSI_TCR_TSCKP (0x00000008)
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#define SSI_TCR_TFSI (0x00000004)
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#define SSI_TCR_TFSL (0x00000002)
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#define SSI_TCR_TEFS (0x00000001)
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#define SSI_RCR_RXEXT (0x00000400)
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#define SSI_RCR_RXBIT0 (0x00000200)
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#define SSI_RCR_RFEN1 (0x00000100)
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#define SSI_RCR_RFEN0 (0x00000080)
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#define SSI_RCR_RSHFD (0x00000010)
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#define SSI_RCR_RSCKP (0x00000008)
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#define SSI_RCR_RFSI (0x00000004)
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#define SSI_RCR_RFSL (0x00000002)
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#define SSI_RCR_REFS (0x00000001)
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#define SSI_CCR_DIV2 (0x00040000)
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#define SSI_CCR_PSR (0x00020000)
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#define SSI_CCR_WL(x) (((x) & 0x0F) << 13)
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#define SSI_CCR_WL_MASK (0xFFFE1FFF)
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#define SSI_CCR_DC(x) (((x)& 0x1F) << 8)
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#define SSI_CCR_DC_MASK (0xFFFFE0FF)
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#define SSI_CCR_PM(x) ((x) & 0xFF)
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#define SSI_CCR_PM_MASK (0xFFFFFF00)
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#define SSI_FCSR_RFCNT1(x) (((x) & 0x0F) << 28)
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#define SSI_FCSR_RFCNT1_MASK (0x0FFFFFFF)
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#define SSI_FCSR_TFCNT1(x) (((x) & 0x0F) << 24)
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#define SSI_FCSR_TFCNT1_MASK (0xF0FFFFFF)
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#define SSI_FCSR_RFWM1(x) (((x) & 0x0F) << 20)
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#define SSI_FCSR_RFWM1_MASK (0xFF0FFFFF)
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#define SSI_FCSR_TFWM1(x) (((x) & 0x0F) << 16)
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#define SSI_FCSR_TFWM1_MASK (0xFFF0FFFF)
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#define SSI_FCSR_RFCNT0(x) (((x) & 0x0F) << 12)
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#define SSI_FCSR_RFCNT0_MASK (0xFFFF0FFF)
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#define SSI_FCSR_TFCNT0(x) (((x) & 0x0F) << 8)
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#define SSI_FCSR_TFCNT0_MASK (0xFFFFF0FF)
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#define SSI_FCSR_RFWM0(x) (((x) & 0x0F) << 4)
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#define SSI_FCSR_RFWM0_MASK (0xFFFFFF0F)
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#define SSI_FCSR_TFWM0(x) ((x) & 0x0F)
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#define SSI_FCSR_TFWM0_MASK (0xFFFFFFF0)
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#define SSI_ACR_FRDIV(x) (((x) & 0x3F) << 5)
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#define SSI_ACR_FRDIV_MASK (0xFFFFF81F)
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#define SSI_ACR_WR (0x00000010)
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#define SSI_ACR_RD (0x00000008)
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#define SSI_ACR_TIF (0x00000004)
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#define SSI_ACR_FV (0x00000002)
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#define SSI_ACR_AC97EN (0x00000001)
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#define SSI_ACADD_SSI_ACADD(x) ((x) & 0x0007FFFF)
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#define SSI_ACDAT_SSI_ACDAT(x) ((x) & 0x0007FFFF)
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#define SSI_ATAG_DDI_ATAG(x) ((x) & 0x0000FFFF)
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#endif /* __SSI_H__ */
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