upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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260 lines
6.8 KiB
260 lines
6.8 KiB
/*
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <spd_sdram.h>
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long int fixed_sdram (void);
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int board_pre_init (void)
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{
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#if defined(CONFIG_PCI)
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volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
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pci->peer &= 0xffffffdf; /* disable master abort */
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#endif
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return 0;
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}
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info (&sysinfo);
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printf ("Board: Freescale MPC8540EVAL Board\n");
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printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
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printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
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printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
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if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
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|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
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printf ("\tLBC: %lu MHz\n",
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sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
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} else {
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printf("\tLBC: unknown\n");
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}
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printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
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return (0);
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}
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phys_size_t initdram (int board_type)
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{
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long dram_size = 0;
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#if !defined(CONFIG_RAM_AS_FLASH)
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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sys_info_t sysinfo;
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uint temp_lbcdll = 0;
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#endif
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#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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#if defined(CONFIG_DDR_DLL)
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uint temp_ddrdll = 0;
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/* Work around to stabilize DDR DLL */
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temp_ddrdll = gur->ddrdllcr;
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gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
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asm("sync;isync;msync");
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#else
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dram_size = fixed_sdram ();
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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return dram_size;
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#endif
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#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
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get_sys_info(&sysinfo);
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/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
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if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
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lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
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} else {
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
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udelay(200);
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temp_lbcdll = gur->lbcdllcr;
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gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
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asm("sync;isync;msync");
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}
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lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
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lbc->br2 = CONFIG_SYS_BR2_PRELIM;
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
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asm("sync");
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* (ulong *)0 = 0x000000ff;
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
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asm("sync");
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* (ulong *)0 = 0x000000ff;
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
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asm("sync");
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* (ulong *)0 = 0x000000ff;
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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asm("sync");
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* (ulong *)0 = 0x000000ff;
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
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asm("sync");
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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asm("sync");
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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asm("sync");
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#endif
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#if defined(CONFIG_DDR_ECC)
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{
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/* Initialize all of memory for ECC, then
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* enable errors */
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uint *p = 0;
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uint i = 0;
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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for (*p = 0; p < (uint *)(8 * 1024); p++) {
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if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
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*p = (unsigned int)0xdeadbeef;
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if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
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}
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/* 8K */
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dmacpy(0x2000, 0, 0x2000);
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/* 16K */
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dmacpy(0x4000, 0, 0x4000);
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/* 32K */
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dmacpy(0x8000, 0, 0x8000);
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/* 64K */
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dmacpy(0x10000, 0, 0x10000);
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/* 128k */
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dmacpy(0x20000, 0, 0x20000);
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/* 256k */
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dmacpy(0x40000, 0, 0x40000);
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/* 512k */
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dmacpy(0x80000, 0, 0x80000);
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/* 1M */
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dmacpy(0x100000, 0, 0x100000);
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/* 2M */
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dmacpy(0x200000, 0, 0x200000);
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/* 4M */
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dmacpy(0x400000, 0, 0x400000);
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for (i = 1; i < dram_size / 0x800000; i++)
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dmacpy(0x800000 * i, 0, 0x800000);
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/* Enable errors for ECC */
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ddr->err_disable = 0x00000000;
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asm("sync;isync;msync");
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}
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#endif
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return dram_size;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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long int fixed_sdram (void)
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{
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#ifndef CONFIG_SYS_RAMBOOT
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000000D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync;msync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#endif
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asm("sync; isync; msync");
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udelay(500);
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#endif
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return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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int board_eth_init(bd_t *bis)
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{
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/*
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* This board either has PCI NICs or uses the CPU's TSECs
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* pci_eth_init() will return 0 if no NICs found, so in that case
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* returning -1 will force cpu_eth_init() to be called.
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*/
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int num = pci_eth_init(bis);
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return (num <= 0 ? -1 : num);
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}
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