upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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112 lines
2.9 KiB
112 lines
2.9 KiB
/*
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_dma.h>
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/* Controller can only transfer 2^26 - 1 bytes at a time */
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#define FSL_DMA_MAX_SIZE (0x3ffffff)
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#if defined(CONFIG_MPC85xx)
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ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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#elif defined(CONFIG_MPC86xx)
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ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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#else
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#error "Freescale DMA engine not supported on your processor"
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#endif
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static void dma_sync(void)
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{
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#if defined(CONFIG_MPC85xx)
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asm("sync; isync; msync");
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#elif defined(CONFIG_MPC86xx)
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asm("sync; isync");
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#endif
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}
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static uint dma_check(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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uint status;
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/* While the channel is busy, spin */
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do {
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status = in_be32(&dma->sr);
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} while (status & FSL_DMA_SR_CB);
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/* clear MR[CS] channel start bit */
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out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
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dma_sync();
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if (status != 0)
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printf ("DMA Error: status = %x\n", status);
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return status;
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}
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void dma_init(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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out_be32(&dma->satr, FSL_DMA_SATR_SREAD_NO_SNOOP);
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out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_NO_SNOOP);
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out_be32(&dma->sr, 0xffffffff); /* clear any errors */
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dma_sync();
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}
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int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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uint xfer_size;
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while (count) {
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xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
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out_be32(&dma->dar, (uint) dest);
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out_be32(&dma->sar, (uint) src);
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out_be32(&dma->bcr, xfer_size);
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/* Disable bandwidth control, use direct transfer mode */
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out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
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dma_sync();
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/* Start the transfer */
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out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
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FSL_DMA_MR_CTM_DIRECT |
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FSL_DMA_MR_CS);
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count -= xfer_size;
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src += xfer_size;
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dest += xfer_size;
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dma_sync();
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if (dma_check())
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return -1;
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}
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return 0;
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}
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