upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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41 lines
1.3 KiB
41 lines
1.3 KiB
/*
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* Copyright (C) 2016 Socionext Inc.
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*/
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#ifndef _DDRPHY_LD20_REGS_H
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#define _DDRPHY_LD20_REGS_H
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#define PHY_SCL_DATA_0 0x00000104
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#define PHY_SCL_DATA_1 0x00000108
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#define PHY_SCL_LATENCY 0x0000010C
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#define PHY_SCL_START 0x00000100
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#define PHY_SCL_CONFIG_1 0x00000118
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#define PHY_SCL_CONFIG_2 0x0000011C
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#define PHY_PAD_CTRL 0x00000120
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#define PHY_DLL_RECALIB 0x00000124
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#define PHY_DLL_ADRCTRL 0x00000128
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#define PHY_LANE_SEL 0x0000012C
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#define PHY_DLL_TRIM_1 0x00000130
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#define PHY_DLL_TRIM_2 0x00000134
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#define PHY_DLL_TRIM_3 0x00000138
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#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
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#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
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#define PHY_WRLVL_DYN_ODT 0x00000150
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#define PHY_WRLVL_ON_OFF 0x00000154
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#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
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#define PHY_DLL_INCR_TRIM_1 0x00000164
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#define PHY_DLL_INCR_TRIM_3 0x00000168
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#define PHY_SCL_CONFIG_3 0x0000016C
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#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
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#define PHY_SCL_START_ADDR 0x00000188
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#define PHY_DSCL_CNT 0x0000019C
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#define PHY_DLL_TRIM_CLK 0x000001A4
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#define PHY_DYNAMIC_BIT_LVL 0x000001AC
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#define PHY_SCL_WINDOW_TRIM 0x000001B4
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#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
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#define PHY_SCL_CONFIG_4 0x000001BC
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#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
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#define PHY_VREF_TRAINING 0x000001C8
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#define PHY_SCL_GATE_TIMING 0x000001E0
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#endif /* _DDRPHY_LD20_REGS_H */
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