upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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120 lines
2.7 KiB
120 lines
2.7 KiB
/*
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* mux.c
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*
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* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux uart1_pin_mux[] = {
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{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
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{-1},
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};
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static struct module_pin_mux uart2_pin_mux[] = {
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{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
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{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
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{-1},
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};
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static struct module_pin_mux uart3_pin_mux[] = {
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{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
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{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
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{-1},
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};
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static struct module_pin_mux uart4_pin_mux[] = {
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{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
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{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
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{-1},
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};
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static struct module_pin_mux uart5_pin_mux[] = {
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{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
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{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
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PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_uart1_pin_mux(void)
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{
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configure_module_pin_mux(uart1_pin_mux);
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}
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void enable_uart2_pin_mux(void)
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{
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configure_module_pin_mux(uart2_pin_mux);
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}
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void enable_uart3_pin_mux(void)
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{
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configure_module_pin_mux(uart3_pin_mux);
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}
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void enable_uart4_pin_mux(void)
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{
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configure_module_pin_mux(uart4_pin_mux);
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}
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void enable_uart5_pin_mux(void)
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{
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configure_module_pin_mux(uart5_pin_mux);
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}
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void enable_uart_pin_mux(u32 addr)
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{
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switch (addr) {
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case CONFIG_SYS_NS16550_COM1:
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enable_uart0_pin_mux();
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break;
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case CONFIG_SYS_NS16550_COM2:
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enable_uart1_pin_mux();
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break;
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case CONFIG_SYS_NS16550_COM3:
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enable_uart2_pin_mux();
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break;
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case CONFIG_SYS_NS16550_COM4:
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enable_uart3_pin_mux();
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break;
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case CONFIG_SYS_NS16550_COM5:
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enable_uart4_pin_mux();
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break;
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case CONFIG_SYS_NS16550_COM6:
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enable_uart5_pin_mux();
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break;
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}
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}
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void enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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