upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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342 lines
9.7 KiB
342 lines
9.7 KiB
/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Device Tree file for Marvell Armada CP110 Slave.
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*/
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#include <dt-bindings/comphy/comphy_data.h>
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/ {
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cp110-slave {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf4000000 0x2000000>;
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cps_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
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clock-names = "pp_clk", "gop_clk", "mg_clk";
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status = "disabled";
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dma-coherent;
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cps_eth0: eth0 {
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interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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cps_eth1: eth1 {
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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cps_eth2: eth2 {
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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cps_mdio: mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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};
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cps_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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reg = <0x440000 0x1000>;
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#clock-cells = <2>;
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core-clock-output-names =
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"cps-apll", "cps-ppv2-core", "cps-eip",
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"cps-core", "cps-nand-core";
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gate-clock-output-names =
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"cps-audio", "cps-communit", "cps-nand",
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"cps-ppv2", "cps-sdio", "cps-mg-domain",
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"cps-mg-core", "cps-xor1", "cps-xor0",
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"cps-gop-dp", "none", "cps-pcie_x10",
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"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
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"cps-sata", "cps-sata-usb", "cps-main",
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"cps-sd-mmc", "none", "none",
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"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
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"cps-usb3dev", "cps-eip150", "cps-eip197";
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};
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cps_pinctl: cps-pinctl@440000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,armada-8k-cps-pinctrl";
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bank-name ="cp1-110";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7
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8 9 10 11 >;
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marvell,function = <3>;
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};
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cps_spi1_pins: cps-spi-pins-1 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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};
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cps_gpio0: gpio@440100 {
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compatible = "marvell,orion-gpio";
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reg = <0x440100 0x40>;
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ngpios = <32>;
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gpiobase = <20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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cps_gpio1: gpio@440140 {
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compatible = "marvell,orion-gpio";
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reg = <0x440140 0x40>;
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ngpios = <31>;
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gpiobase = <52>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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cps_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 15>;
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status = "disabled";
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};
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cps_usb3_0: usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 22>;
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status = "disabled";
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};
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cps_usb3_1: usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 23>;
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status = "disabled";
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};
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cps_xor0: xor@6a0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6a0000 0x1000>,
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<0x6b0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cps_syscon0 1 8>;
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};
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cps_xor1: xor@6c0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6c0000 0x1000>,
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<0x6d0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cps_syscon0 1 7>;
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};
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cps_spi0: spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cell-index = <1>;
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clocks = <&cps_syscon0 0 3>;
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status = "disabled";
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};
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cps_spi1: spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_i2c0: i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_i2c1: i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cps_syscon0 1 21>;
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status = "disabled";
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};
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cps_comphy: comphy@441000 {
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compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
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reg = <0x441000 0x8>,
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<0x120000 0x8>;
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mux-bitcount = <4>;
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max-lanes = <6>;
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};
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cps_utmi0: utmi@580000 {
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compatible = "marvell,mvebu-utmi-2.6.0";
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reg = <0x580000 0x1000>, /* utmi-unit */
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<0x440420 0x4>, /* usb-cfg */
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<0x440440 0x4>; /* utmi-cfg */
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utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
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status = "disabled";
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};
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};
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cps_pcie0: pcie@f4600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4600000 0 0x10000>,
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<0 0xfaf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 13>;
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status = "disabled";
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};
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cps_pcie1: pcie@f4620000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4620000 0 0x10000>,
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<0 0xfbf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 11>;
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status = "disabled";
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};
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cps_pcie2: pcie@f4640000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf4640000 0 0x10000>,
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<0 0xfcf00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cps_syscon0 1 12>;
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status = "disabled";
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};
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};
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};
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