upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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100 lines
3.2 KiB
100 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#ifndef _LPC32XX_UART_H
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#define _LPC32XX_UART_H
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#include <asm/types.h>
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/* 14-clock UART Registers */
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struct hsuart_regs {
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union {
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u32 rx; /* Receiver FIFO */
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u32 tx; /* Transmitter FIFO */
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};
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u32 level; /* FIFO Level Register */
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u32 iir; /* Interrupt ID Register */
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u32 ctrl; /* Control Register */
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u32 rate; /* Rate Control Register */
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};
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/* 14-clock UART Receiver FIFO Register bits */
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#define HSUART_RX_BREAK (1 << 10)
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#define HSUART_RX_ERROR (1 << 9)
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#define HSUART_RX_EMPTY (1 << 8)
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#define HSUART_RX_DATA (0xff << 0)
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/* 14-clock UART Level Register bits */
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#define HSUART_LEVEL_TX (0xff << 8)
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#define HSUART_LEVEL_RX (0xff << 0)
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/* 14-clock UART Interrupt Identification Register bits */
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#define HSUART_IIR_TX_INT_SET (1 << 6)
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#define HSUART_IIR_RX_OE (1 << 5)
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#define HSUART_IIR_BRK (1 << 4)
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#define HSUART_IIR_FE (1 << 3)
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#define HSUART_IIR_RX_TIMEOUT (1 << 2)
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#define HSUART_IIR_RX_TRIG (1 << 1)
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#define HSUART_IIR_TX (1 << 0)
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/* 14-clock UART Control Register bits */
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#define HSUART_CTRL_HRTS_INV (1 << 21)
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#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19)
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#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19)
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#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19)
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#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19)
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#define HSUART_CTRL_HRTS_EN (1 << 18)
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#define HSUART_CTRL_TMO_16 (0x3 << 16)
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#define HSUART_CTRL_TMO_8 (0x2 << 16)
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#define HSUART_CTRL_TMO_4 (0x1 << 16)
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#define HSUART_CTRL_TMO_DISABLED (0x0 << 16)
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#define HSUART_CTRL_HCTS_INV (1 << 15)
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#define HSUART_CTRL_HCTS_EN (1 << 14)
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#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9)
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#define HSUART_CTRL_HSU_BREAK (1 << 8)
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#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7)
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#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6)
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#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5)
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#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2)
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#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2)
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#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0)
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#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0)
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/* UART Control Registers */
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struct uart_ctrl_regs {
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u32 ctrl; /* Control Register */
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u32 clkmode; /* Clock Mode Register */
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u32 loop; /* Loopback Control Register */
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};
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/* UART Control Register bits */
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#define UART_CTRL_UART3_MD_CTRL (1 << 11)
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#define UART_CTRL_HDPX_INV (1 << 10)
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#define UART_CTRL_HDPX_EN (1 << 9)
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#define UART_CTRL_UART6_IRDA (1 << 5)
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#define UART_CTRL_IR_TX6_INV (1 << 4)
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#define UART_CTRL_IR_RX6_INV (1 << 3)
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#define UART_CTRL_IR_RX_LENGTH (1 << 2)
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#define UART_CTRL_IR_TX_LENGTH (1 << 1)
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#define UART_CTRL_UART5_USB_MODE (1 << 0)
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/* UART Clock Mode Register bits */
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#define UART_CLKMODE_STATX(n) (1 << ((n) + 16))
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#define UART_CLKMODE_STAT (1 << 14)
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#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2))
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#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2))
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#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2))
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#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))
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/* UART Loopback Control Register bits */
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#define UART_LOOPBACK(n) (1 << ((n) - 1))
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#endif /* _LPC32XX_UART_H */
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