upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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303 lines
6.2 KiB
303 lines
6.2 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <led.h>
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#include <malloc.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pmu_rk3288.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/sdram_common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <dm/test.h>
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#include <dm/util.h>
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#include <power/regulator.h>
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#include <power/rk8xx_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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const void *blob = gd->fdt_blob;
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struct udevice *dev;
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const char *bootdev;
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int node;
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int ret;
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bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
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debug("Boot device %s\n", bootdev);
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if (!bootdev)
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goto fallback;
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node = fdt_path_offset(blob, bootdev);
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if (node < 0) {
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debug("node=%d\n", node);
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goto fallback;
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}
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ret = device_get_global_by_of_offset(node, &dev);
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if (ret) {
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debug("device at node %s/%d not found: %d\n", bootdev, node,
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ret);
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goto fallback;
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}
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debug("Found device %s\n", dev->name);
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switch (device_get_uclass_id(dev)) {
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case UCLASS_SPI_FLASH:
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return BOOT_DEVICE_SPI;
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case UCLASS_MMC:
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return BOOT_DEVICE_MMC1;
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default:
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debug("Booting from device uclass '%s' not supported\n",
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dev_get_uclass_name(dev));
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}
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fallback:
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#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
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defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
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defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
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return BOOT_DEVICE_SPI;
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#endif
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return BOOT_DEVICE_MMC1;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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static int configure_emmc(struct udevice *pinctrl)
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{
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#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
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struct gpio_desc desc;
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int ret;
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pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
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/*
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* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
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* use the EMMC_PWREN setting.
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*/
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ret = dm_gpio_lookup_name("D9", &desc);
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if (ret) {
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debug("gpio ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_request(&desc, "emmc_pwren");
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if (ret) {
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debug("gpio_request ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
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if (ret) {
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debug("gpio dir ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_value(&desc, 1);
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if (ret) {
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debug("gpio value ret=%d\n", ret);
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return ret;
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}
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#endif
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPL_OF_PLATDATA)
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static int phycore_init(void)
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{
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struct udevice *pmic;
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int ret;
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ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
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if (ret)
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return ret;
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#if defined(CONFIG_SPL_POWER_SUPPORT)
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/* Increase USB input current to 2A */
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ret = rk818_spl_configure_usb_input_current(pmic, 2000);
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if (ret)
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return ret;
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/* Close charger when USB lower then 3.26V */
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ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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struct udevice *pinctrl;
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struct udevice *dev;
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int ret;
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/* Example code showing how to enable the debug UART on RK3288 */
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#include <asm/arch/grf_rk3288.h>
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/* Enable early UART on the RK3288 */
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#define GRF_BASE 0xff770000
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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debug("\nspl:debug uart enabled in %s\n", __func__);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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rockchip_timer_init();
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configure_l2ctlr();
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ret = rockchip_get_clk(&dev);
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if (ret) {
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debug("CLK init failed: %d\n", ret);
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return;
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("Pinctrl init failed: %d\n", ret);
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return;
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}
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#if !defined(CONFIG_SPL_OF_PLATDATA)
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if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
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ret = phycore_init();
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if (ret) {
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debug("Failed to set up phycore power settings: %d\n",
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ret);
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return;
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}
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}
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#endif
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#if !defined(CONFIG_SUPPORT_TPL)
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debug("\nspl:init dram\n");
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return;
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}
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#endif
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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}
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static int setup_led(void)
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{
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#ifdef CONFIG_SPL_LED
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struct udevice *dev;
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
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if (!led_name)
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return 0;
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ret = led_get_by_label(led_name, &dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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ret = led_set_on(dev, 1);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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void spl_board_init(void)
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{
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struct udevice *pinctrl;
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int ret;
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ret = setup_led();
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if (ret) {
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debug("LED ret=%d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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goto err;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
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if (ret) {
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debug("%s: Failed to set up SD card\n", __func__);
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goto err;
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}
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ret = configure_emmc(pinctrl);
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if (ret) {
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debug("%s: Failed to set up eMMC\n", __func__);
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goto err;
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}
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#endif
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/* Enable debug UART */
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
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if (ret) {
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debug("%s: Failed to set up console UART\n", __func__);
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goto err;
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}
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preloader_console_init();
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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return;
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err:
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printf("spl_board_init: Error %d\n", ret);
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/* No way to report error here */
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hang();
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}
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#ifdef CONFIG_SPL_OS_BOOT
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#define PMU_BASE 0xff730000
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int dram_init_banksize(void)
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{
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struct rk3288_pmu *const pmu = (void *)PMU_BASE;
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size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = size;
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return 0;
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}
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#endif
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