upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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128 lines
3.3 KiB
128 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TLMM driver for Qualcomm APQ8016, APQ8096
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*
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* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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#include "pinctrl-snapdragon.h"
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struct msm_pinctrl_priv {
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phys_addr_t base;
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struct msm_pinctrl_data *data;
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};
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#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
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#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
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#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
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#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
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#define TLMM_GPIO_ENABLE BIT(9)
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static const struct pinconf_param msm_conf_params[] = {
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{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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};
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static int msm_get_functions_count(struct udevice *dev)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->data->functions_count;
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}
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static int msm_get_pins_count(struct udevice *dev)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->data->pin_count;
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}
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static const char *msm_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->data->get_function_name(dev, selector);
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}
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static int msm_pinctrl_probe(struct udevice *dev)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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priv->base = devfdt_get_addr(dev);
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priv->data = (struct msm_pinctrl_data *)dev->driver_data;
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return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
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}
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static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->data->get_pin_name(dev, selector);
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}
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static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
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unsigned int func_selector)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
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TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
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priv->data->get_function_mux(func_selector) << 2);
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return 0;
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}
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static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
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unsigned int param, unsigned int argument)
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{
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struct msm_pinctrl_priv *priv = dev_get_priv(dev);
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
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TLMM_DRV_STRENGTH_MASK, argument << 6);
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
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TLMM_GPIO_PULL_MASK);
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break;
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default:
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return 0;
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}
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return 0;
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}
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static struct pinctrl_ops msm_pinctrl_ops = {
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.get_pins_count = msm_get_pins_count,
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.get_pin_name = msm_get_pin_name,
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.set_state = pinctrl_generic_set_state,
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.pinmux_set = msm_pinmux_set,
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.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
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.pinconf_params = msm_conf_params,
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.pinconf_set = msm_pinconf_set,
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.get_functions_count = msm_get_functions_count,
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.get_function_name = msm_get_function_name,
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};
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static const struct udevice_id msm_pinctrl_ids[] = {
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{ .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
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{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_snapdraon) = {
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.name = "pinctrl_msm",
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.id = UCLASS_PINCTRL,
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.of_match = msm_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
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.ops = &msm_pinctrl_ops,
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.probe = msm_pinctrl_probe,
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};
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