upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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109 lines
2.7 KiB
109 lines
2.7 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
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* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
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*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* (C) Copyright 2004
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* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
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*
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* (C) Copyright 2002-2004
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* (C) Copyright 2003
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* Texas Instruments <www.ti.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*/
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#include <clk.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct scu_timer {
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u32 load; /* Timer Load Register */
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u32 counter; /* Timer Counter Register */
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u32 control; /* Timer Control Register */
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};
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static struct scu_timer *timer_base =
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(struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
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#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
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#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
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#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */
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#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */
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#define TIMER_LOAD_VAL 0xFFFFFFFF
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#define TIMER_PRESCALE 255
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int timer_init(void)
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{
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const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
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(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
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SCUTIMER_CONTROL_ENABLE_MASK;
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(zynq_clk), &dev);
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if (ret)
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return ret;
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clk.id = cpu_6or4x_clk;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return ret;
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gd->cpu_clk = clk_get_rate(&clk);
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clk_free(&clk);
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gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
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/* Load the timer counter register */
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writel(0xFFFFFFFF, &timer_base->load);
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/*
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* Start the A9Timer device
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* Enable Auto reload mode, Clear prescaler control bits
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* Set prescaler value, Enable the decrementer
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*/
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clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
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emask);
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/* Reset time */
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gd->arch.lastinc = readl(&timer_base->counter) /
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(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
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gd->arch.tbl = 0;
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return 0;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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