upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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306 lines
9.5 KiB
306 lines
9.5 KiB
/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS2_COMMON_H
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#define __LS2_COMMON_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_FSL_LSCH3
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#define CONFIG_MP
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#define CONFIG_GICV3
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#define CONFIG_FSL_TZPC_BP147
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#include <asm/arch/ls2080a_stream_id.h>
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#include <asm/arch/config.h>
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#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
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#define CONFIG_SYS_HAS_SERDES
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#endif
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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/* We need architecture specific misc initializations */
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#define CONFIG_ARCH_MISC_INIT
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/* Link Definitions */
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#ifdef CONFIG_SPL
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#define CONFIG_SYS_TEXT_BASE 0x80400000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x30100000
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#endif
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#ifdef CONFIG_EMU
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#define CONFIG_SYS_NO_FLASH
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#endif
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#ifndef CONFIG_SPL
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#endif
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#ifndef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
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#define CONFIG_SYS_DDR_RAW_TIMING
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#endif
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#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
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/*
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* SMP Definitinos
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*/
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#define CPU_RELEASE_ADDR secondary_boot_func
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#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
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/*
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* DDR controller use 0 as the base address for binding.
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* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
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*/
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#define CONFIG_SYS_DP_DDR_BASE_PHY 0
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#define CONFIG_DP_DDR_CTRL 2
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#define CONFIG_DP_DDR_NUM_CTRLS 1
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#endif
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/* Generic Timer Definitions */
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/*
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* This is not an accurate number. It is used in start.S. The frequency
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* will be udpated later when get_bus_freq(0) is available.
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*/
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* I2C */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* During booting, IFC is mapped at the region of 0x30000000.
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* But this region is limited to 256MB. To accommodate NOR, promjet
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* and FPGA. This region is divided as below:
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* 0x30000000 - 0x37ffffff : 128MB : NOR flash
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* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
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* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
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*
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* To accommodate bigger NOR flash and other devices, we will map IFC
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* chip selects to as below:
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* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
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* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
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* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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*
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* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
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*/
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#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
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#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
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#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
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#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
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#ifndef CONFIG_SYS_NO_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#endif
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#ifndef __ASSEMBLY__
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unsigned long long get_qixis_addr(void);
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#endif
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#define QIXIS_BASE get_qixis_addr()
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#define QIXIS_BASE_PHYS 0x20000000
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#define QIXIS_BASE_PHYS_EARLY 0xC000000
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#define QIXIS_STAT_PRES1 0xb
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#define CONFIG_SYS_NAND_BASE 0x530000000ULL
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#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
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/* Debug Server firmware */
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#define CONFIG_FSL_DEBUG_SERVER
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/* 2 sec timeout */
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#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
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/* MC firmware */
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#define CONFIG_FSL_MC_ENET
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/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
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#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
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#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
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/* For LS2085A */
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#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
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#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
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/*
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* Carve out a DDR region which will not be used by u-boot/Linux
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*
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* It will be used by MC and Debug Server. The MC region must be
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* 512MB aligned, so the min size to hide is 512MB.
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*/
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#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
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#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
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#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
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#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
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#endif
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/* PCIe */
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#define CONFIG_PCIE1 /* PCIE controler 1 */
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#define CONFIG_PCIE2 /* PCIE controler 2 */
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#define CONFIG_PCIE3 /* PCIE controler 3 */
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#define CONFIG_PCIE4 /* PCIE controler 4 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#ifdef CONFIG_LS2080A
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#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
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#endif
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
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#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
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#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
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#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
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#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
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#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
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/* Command line configuration */
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_GREPENV
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_ARCH_EARLY_INIT_R
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/* Physical Memory Map */
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/* fixme: these need to be checked against the board */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_NR_DRAM_BANKS 3
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#define CONFIG_DISPLAY_CPUINFO
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581200000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyAMA0,38400n8\0" \
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"mcinitcmd=fsl_mc start mc 0x580300000" \
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" 0x580800000 \0"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
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"earlycon=uart8250,mmio,0x21c0500 " \
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"ramdisk_size=0x2000000 default_hugepagesz=2m" \
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" hugepagesz=2m hugepages=256"
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#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \
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" cp.b $kernel_start $kernel_load" \
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" $kernel_size && bootm $kernel_load"
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#define CONFIG_BOOTDELAY 10
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_MAX_SIZE 0x16000
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0x1800a000
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#endif /* __LS2_COMMON_H */
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