upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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79 lines
1.8 KiB
79 lines
1.8 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Support of SDHCI for Microchip PIC32 SoC.
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*
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* Copyright (C) 2015 Microchip Technology Inc.
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* Andrei Pistirica <andrei.pistirica@microchip.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <sdhci.h>
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#include <linux/errno.h>
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#include <mach/pic32.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int pic32_sdhci_get_cd(struct sdhci_host *host)
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{
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/* PIC32 SDHCI CD errata:
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* - set CD_TEST and clear CD_TEST_INS bit
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*/
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sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
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return 0;
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}
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static const struct sdhci_ops pic32_sdhci_ops = {
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.get_cd = pic32_sdhci_get_cd,
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};
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static int pic32_sdhci_probe(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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const void *fdt = gd->fdt_blob;
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u32 f_min_max[2];
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fdt_addr_t addr;
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fdt_size_t size;
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int ret;
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addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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host->ioaddr = ioremap(addr, size);
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host->name = dev->name;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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host->ops = &pic32_sdhci_ops;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", f_min_max, 2);
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if (ret) {
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printf("sdhci: clock-freq-min-max not found\n");
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return ret;
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}
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host->max_clk = f_min_max[1];
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ret = add_sdhci(host, 0, f_min_max[0]);
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if (ret)
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return ret;
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host->mmc->dev = dev;
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return 0;
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}
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static const struct udevice_id pic32_sdhci_ids[] = {
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{ .compatible = "microchip,pic32mzda-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(pic32_sdhci_drv) = {
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.name = "pic32_sdhci",
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.id = UCLASS_MMC,
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.of_match = pic32_sdhci_ids,
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.probe = pic32_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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};
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