upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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240 lines
6.5 KiB
240 lines
6.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MMCIF driver.
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*/
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#ifndef _SH_MMCIF_H_
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#define _SH_MMCIF_H_
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struct sh_mmcif_regs {
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unsigned long ce_cmd_set;
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unsigned long reserved;
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unsigned long ce_arg;
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unsigned long ce_arg_cmd12;
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unsigned long ce_cmd_ctrl;
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unsigned long ce_block_set;
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unsigned long ce_clk_ctrl;
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unsigned long ce_buf_acc;
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unsigned long ce_resp3;
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unsigned long ce_resp2;
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unsigned long ce_resp1;
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unsigned long ce_resp0;
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unsigned long ce_resp_cmd12;
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unsigned long ce_data;
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unsigned long reserved2[2];
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unsigned long ce_int;
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unsigned long ce_int_mask;
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unsigned long ce_host_sts1;
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unsigned long ce_host_sts2;
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unsigned long reserved3[11];
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unsigned long ce_version;
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};
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/* CE_CMD_SET */
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#define CMD_MASK 0x3f000000
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#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
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/* R1/R1b/R3/R4/R5 */
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#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
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/* R2 */
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#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
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/* R1b */
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#define CMD_SET_RBSY (1 << 21)
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#define CMD_SET_CCSEN (1 << 20)
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/* 1: on data, 0: no data */
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#define CMD_SET_WDAT (1 << 19)
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/* 1: write to card, 0: read from card */
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#define CMD_SET_DWEN (1 << 18)
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/* 1: multi block trans, 0: single */
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#define CMD_SET_CMLTE (1 << 17)
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/* 1: CMD12 auto issue */
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#define CMD_SET_CMD12EN (1 << 16)
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/* index check */
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#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14))
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/* check bits check */
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#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14))
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/* no check */
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#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14))
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/* 1: CRC7 check*/
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#define CMD_SET_CRC7C ((0 << 13) | (0 << 12))
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/* 1: check bits check*/
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#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12))
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/* 1: internal CRC7 check*/
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#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12))
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/* 1: CRC16 check*/
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#define CMD_SET_CRC16C (1 << 10)
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/* 1: not receive CRC status */
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#define CMD_SET_CRCSTE (1 << 8)
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/* 1: tran mission bit "Low" */
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#define CMD_SET_TBIT (1 << 7)
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/* 1: open/drain */
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#define CMD_SET_OPDM (1 << 6)
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#define CMD_SET_CCSH (1 << 5)
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/* 1bit */
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#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0))
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/* 4bit */
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#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0))
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/* 8bit */
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#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0))
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/* CE_CMD_CTRL */
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#define CMD_CTRL_BREAK (1 << 0)
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/* CE_BLOCK_SET */
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#define BLOCK_SIZE_MASK 0x0000ffff
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/* CE_CLK_CTRL */
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#define CLK_ENABLE (1 << 24)
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#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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/* respons timeout */
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#define SRSPTO_256 ((1 << 13) | (0 << 12))
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/* respons busy timeout */
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#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
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/* read/write timeout */
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#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
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/* ccs timeout */
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#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
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/* CE_BUF_ACC */
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#define BUF_ACC_DMAWEN (1 << 25)
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#define BUF_ACC_DMAREN (1 << 24)
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#define BUF_ACC_BUSW_32 (0 << 17)
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#define BUF_ACC_BUSW_16 (1 << 17)
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#define BUF_ACC_ATYP (1 << 16)
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/* CE_INT */
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#define INT_CCSDE (1 << 29)
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#define INT_CMD12DRE (1 << 26)
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#define INT_CMD12RBE (1 << 25)
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#define INT_CMD12CRE (1 << 24)
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#define INT_DTRANE (1 << 23)
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#define INT_BUFRE (1 << 22)
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#define INT_BUFWEN (1 << 21)
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#define INT_BUFREN (1 << 20)
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#define INT_CCSRCV (1 << 19)
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#define INT_RBSYE (1 << 17)
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#define INT_CRSPE (1 << 16)
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#define INT_CMDVIO (1 << 15)
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#define INT_BUFVIO (1 << 14)
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#define INT_WDATERR (1 << 11)
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#define INT_RDATERR (1 << 10)
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#define INT_RIDXERR (1 << 9)
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#define INT_RSPERR (1 << 8)
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#define INT_CCSTO (1 << 5)
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#define INT_CRCSTO (1 << 4)
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#define INT_WDATTO (1 << 3)
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#define INT_RDATTO (1 << 2)
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#define INT_RBSYTO (1 << 1)
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#define INT_RSPTO (1 << 0)
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#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
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INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
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INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
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INT_RDATTO | INT_RBSYTO | INT_RSPTO)
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#define INT_START_MAGIC 0xD80430C0
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/* CE_INT_MASK */
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#define MASK_ALL 0x00000000
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#define MASK_MCCSDE (1 << 29)
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#define MASK_MCMD12DRE (1 << 26)
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#define MASK_MCMD12RBE (1 << 25)
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#define MASK_MCMD12CRE (1 << 24)
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#define MASK_MDTRANE (1 << 23)
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#define MASK_MBUFRE (1 << 22)
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#define MASK_MBUFWEN (1 << 21)
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#define MASK_MBUFREN (1 << 20)
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#define MASK_MCCSRCV (1 << 19)
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#define MASK_MRBSYE (1 << 17)
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#define MASK_MCRSPE (1 << 16)
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#define MASK_MCMDVIO (1 << 15)
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#define MASK_MBUFVIO (1 << 14)
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#define MASK_MWDATERR (1 << 11)
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#define MASK_MRDATERR (1 << 10)
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#define MASK_MRIDXERR (1 << 9)
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#define MASK_MRSPERR (1 << 8)
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#define MASK_MCCSTO (1 << 5)
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#define MASK_MCRCSTO (1 << 4)
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#define MASK_MWDATTO (1 << 3)
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#define MASK_MRDATTO (1 << 2)
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#define MASK_MRBSYTO (1 << 1)
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#define MASK_MRSPTO (1 << 0)
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/* CE_HOST_STS1 */
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#define STS1_CMDSEQ (1 << 31)
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/* CE_HOST_STS2 */
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#define STS2_CRCSTE (1 << 31)
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#define STS2_CRC16E (1 << 30)
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#define STS2_AC12CRCE (1 << 29)
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#define STS2_RSPCRC7E (1 << 28)
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#define STS2_CRCSTEBE (1 << 27)
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#define STS2_RDATEBE (1 << 26)
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#define STS2_AC12REBE (1 << 25)
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#define STS2_RSPEBE (1 << 24)
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#define STS2_AC12IDXE (1 << 23)
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#define STS2_RSPIDXE (1 << 22)
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#define STS2_CCSTO (1 << 15)
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#define STS2_RDATTO (1 << 14)
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#define STS2_DATBSYTO (1 << 13)
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#define STS2_CRCSTTO (1 << 12)
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#define STS2_AC12BSYTO (1 << 11)
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#define STS2_RSPBSYTO (1 << 10)
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#define STS2_AC12RSPTO (1 << 9)
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#define STS2_RSPTO (1 << 8)
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#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
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STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
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#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
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STS2_DATBSYTO | STS2_CRCSTTO | \
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STS2_AC12BSYTO | STS2_RSPBSYTO | \
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STS2_AC12RSPTO | STS2_RSPTO)
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/* CE_VERSION */
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#define SOFT_RST_ON (1 << 31)
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#define SOFT_RST_OFF (0 << 31)
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#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
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#ifdef CONFIG_ARCH_RMOBILE
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#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
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#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
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#else
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#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 8))
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#define MMC_CLK_DIV_MAX(clk) CLKDEV_EMMC_DATA
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#endif
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#define MMC_BUS_WIDTH_1 0
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#define MMC_BUS_WIDTH_4 2
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#define MMC_BUS_WIDTH_8 3
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struct sh_mmcif_host {
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struct mmc_data *data;
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struct sh_mmcif_regs *regs;
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unsigned int clk;
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int bus_width;
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u16 wait_int;
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u16 sd_error;
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u8 last_cmd;
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};
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static inline u32 sh_mmcif_read(unsigned long *reg)
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{
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return readl(reg);
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}
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static inline void sh_mmcif_write(u32 val, unsigned long *reg)
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{
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writel(val, reg);
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}
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static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
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{
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sh_mmcif_write(val | sh_mmcif_read(reg), reg);
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}
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static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
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{
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sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
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}
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#endif /* _SH_MMCIF_H_ */
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