upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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402 lines
11 KiB
402 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI autoconfiguration library (legacy version, do not change)
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000 MontaVista Software Inc.
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*/
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#include <common.h>
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#include <errno.h>
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#include <pci.h>
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/*
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* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
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* and change pci_auto.c.
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*/
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/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
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#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
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#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
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#endif
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/*
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*
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*/
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void pciauto_setup_device(struct pci_controller *hose,
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pci_dev_t dev, int bars_num,
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struct pci_region *mem,
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struct pci_region *prefetch,
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struct pci_region *io)
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{
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u32 bar_response;
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pci_size_t bar_size;
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u16 cmdstat = 0;
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int bar, bar_nr = 0;
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#ifndef CONFIG_PCI_ENUM_ONLY
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u8 header_type;
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int rom_addr;
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pci_addr_t bar_value;
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struct pci_region *bar_res;
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int found_mem64 = 0;
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#endif
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u16 class;
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
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cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
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for (bar = PCI_BASE_ADDRESS_0;
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bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
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/* Tickle the BAR and get the response */
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#ifndef CONFIG_PCI_ENUM_ONLY
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pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
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#endif
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pci_hose_read_config_dword(hose, dev, bar, &bar_response);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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#ifndef CONFIG_PCI_ENUM_ONLY
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found_mem64 = 0;
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#endif
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
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& 0xffff) + 1;
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#ifndef CONFIG_PCI_ENUM_ONLY
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bar_res = io;
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#endif
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debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
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bar_nr, (unsigned long long)bar_size);
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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u32 bar_response_upper;
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u64 bar64;
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#ifndef CONFIG_PCI_ENUM_ONLY
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pci_hose_write_config_dword(hose, dev, bar + 4,
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0xffffffff);
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#endif
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pci_hose_read_config_dword(hose, dev, bar + 4,
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&bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) | bar_response;
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bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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#ifndef CONFIG_PCI_ENUM_ONLY
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found_mem64 = 1;
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#endif
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} else {
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bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
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}
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#ifndef CONFIG_PCI_ENUM_ONLY
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if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
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bar_res = prefetch;
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else
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bar_res = mem;
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debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
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bar_nr, bar_res == prefetch ? "Prf" : "Mem",
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(unsigned long long)bar_size);
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#endif
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}
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#ifndef CONFIG_PCI_ENUM_ONLY
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if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
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/* Write it out and update our limit */
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pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
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if (found_mem64) {
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
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#else
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/*
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* If we are a 64-bit decoder then increment to the
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* upper 32 bits of the bar and force it to locate
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* in the lower 4GB of memory.
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*/
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pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
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#endif
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}
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}
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#endif
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cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
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PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
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debug("\n");
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bar_nr++;
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}
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#ifndef CONFIG_PCI_ENUM_ONLY
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/* Configure the expansion ROM address */
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pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
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header_type &= 0x7f;
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if (header_type != PCI_HEADER_TYPE_CARDBUS) {
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rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
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PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
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pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
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pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
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if (bar_response) {
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bar_size = -(bar_response & ~1);
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debug("PCI Autoconfig: ROM, size=%#x, ",
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(unsigned int)bar_size);
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if (pciauto_region_allocate(mem, bar_size,
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&bar_value) == 0) {
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pci_hose_write_config_dword(hose, dev, rom_addr,
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bar_value);
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}
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cmdstat |= PCI_COMMAND_MEMORY;
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debug("\n");
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}
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}
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#endif
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/* PCI_COMMAND_IO must be set for VGA device */
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pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
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if (class == PCI_CLASS_DISPLAY_VGA)
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cmdstat |= PCI_COMMAND_IO;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
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CONFIG_SYS_PCI_CACHE_LINE_SIZE);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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}
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void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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u16 cmdstat, prefechable_64;
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pci_mem = hose->pci_mem;
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pci_prefetch = hose->pci_prefetch;
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pci_io = hose->pci_io;
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pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
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pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
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&prefechable_64);
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prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
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/* Configure bus number registers */
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pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
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PCI_BUS(dev) - hose->first_busno);
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pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
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sub_bus - hose->first_busno);
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pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
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(pci_mem->bus_lower & 0xfff00000) >> 16);
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (pci_prefetch) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
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(pci_prefetch->bus_lower & 0xfff00000) >> 16);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
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#ifdef CONFIG_SYS_PCI_64BIT
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pci_hose_write_config_dword(hose, dev,
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PCI_PREF_BASE_UPPER32,
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pci_prefetch->bus_lower >> 32);
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#else
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pci_hose_write_config_dword(hose, dev,
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PCI_PREF_BASE_UPPER32,
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0x0);
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#endif
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cmdstat |= PCI_COMMAND_MEMORY;
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} else {
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/* We don't support prefetchable memory for now, so disable */
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
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pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
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pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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}
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
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(pci_io->bus_lower & 0x0000f000) >> 8);
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pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
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(pci_io->bus_lower & 0xffff0000) >> 16);
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cmdstat |= PCI_COMMAND_IO;
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}
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/* Enable memory and I/O accesses, enable bus master */
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pci_hose_write_config_word(hose, dev, PCI_COMMAND,
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cmdstat | PCI_COMMAND_MASTER);
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}
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void pciauto_postscan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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pci_mem = hose->pci_mem;
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pci_prefetch = hose->pci_prefetch;
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pci_io = hose->pci_io;
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/* Configure bus number registers */
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pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
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sub_bus - hose->first_busno);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
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(pci_mem->bus_lower - 1) >> 16);
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}
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if (pci_prefetch) {
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u16 prefechable_64;
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pci_hose_read_config_word(hose, dev,
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PCI_PREF_MEMORY_LIMIT,
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&prefechable_64);
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prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
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(pci_prefetch->bus_lower - 1) >> 16);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
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#ifdef CONFIG_SYS_PCI_64BIT
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pci_hose_write_config_dword(hose, dev,
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PCI_PREF_LIMIT_UPPER32,
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(pci_prefetch->bus_lower - 1) >> 32);
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#else
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pci_hose_write_config_dword(hose, dev,
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PCI_PREF_LIMIT_UPPER32,
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0x0);
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#endif
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
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((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
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pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
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((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
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}
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}
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/*
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* HJF: Changed this to return int. I think this is required
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* to get the correct result when scanning bridges
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*/
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int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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unsigned int sub_bus = PCI_BUS(dev);
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unsigned short class;
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int n;
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pci_mem = hose->pci_mem;
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pci_prefetch = hose->pci_prefetch;
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pci_io = hose->pci_io;
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pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
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switch (class) {
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case PCI_CLASS_BRIDGE_PCI:
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debug("PCI Autoconfig: Found P2P bridge, device %d\n",
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PCI_DEV(dev));
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pciauto_setup_device(hose, dev, 2, pci_mem,
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pci_prefetch, pci_io);
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/* Passing in current_busno allows for sibling P2P bridges */
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hose->current_busno++;
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pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
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/*
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* need to figure out if this is a subordinate bridge on the bus
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* to be able to properly set the pri/sec/sub bridge registers.
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*/
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n = pci_hose_scan_bus(hose, hose->current_busno);
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/* figure out the deepest we've gone for this leg */
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sub_bus = max((unsigned int)n, sub_bus);
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pciauto_postscan_setup_bridge(hose, dev, sub_bus);
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sub_bus = hose->current_busno;
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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/*
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* just do a minimal setup of the bridge,
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* let the OS take care of the rest
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*/
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pciauto_setup_device(hose, dev, 0, pci_mem,
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pci_prefetch, pci_io);
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debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
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PCI_DEV(dev));
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hose->current_busno++;
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break;
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#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
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case PCI_CLASS_BRIDGE_OTHER:
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debug("PCI Autoconfig: Skipping bridge device %d\n",
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PCI_DEV(dev));
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break;
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#endif
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#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
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case PCI_CLASS_BRIDGE_OTHER:
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/*
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* The host/PCI bridge 1 seems broken in 8349 - it presents
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* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
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* device claiming resources io/mem/irq.. we only allow for
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* the PIMMR window to be allocated (BAR0 - 1MB size)
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*/
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debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
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pciauto_setup_device(hose, dev, 0, hose->pci_mem,
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hose->pci_prefetch, hose->pci_io);
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break;
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#endif
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case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
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debug("PCI AutoConfig: Found PowerPC device\n");
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default:
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pciauto_setup_device(hose, dev, 6, pci_mem,
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pci_prefetch, pci_io);
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break;
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}
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return sub_bus;
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}
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