upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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307 lines
8.9 KiB
307 lines
8.9 KiB
/*-----------------------------------------------------------------------------+
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1995
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+-----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------+
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| File Name: miiphy.c
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| Function: This module has utilities for accessing the MII PHY through
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| the EMAC3 macro.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 05-May-99 Created MKW
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| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
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| better match OPB speed. Also modified delay times. JWB
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| 29-Jul-99 Added Full duplex support MKW
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| 24-Aug-99 Removed printf from dp83843_duplex() JWB
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| 19-Jul-00 Ported to esd cpci405 sr
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| 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
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| <travis.sawyer@sandburst.com>
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+-----------------------------------------------------------------------------*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#include <ppc4xx_enet.h>
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#include <405_mal.h>
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#include <miiphy.h>
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#undef ET_DEBUG
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/***********************************************************/
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/* Dump out to the screen PHY regs */
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/***********************************************************/
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void miiphy_dump (char *devname, unsigned char addr)
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{
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unsigned long i;
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unsigned short data;
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for (i = 0; i < 0x1A; i++) {
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if (miiphy_read (devname, addr, i, &data)) {
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printf ("read error for reg %lx\n", i);
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return;
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}
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printf ("Phy reg %lx ==> %4x\n", i, data);
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/* jump to the next set of regs */
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if (i == 0x07)
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i = 0x0f;
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} /* end for loop */
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} /* end dump */
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/***********************************************************/
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/* (Re)start autonegotiation */
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/***********************************************************/
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int phy_setup_aneg (char *devname, unsigned char addr)
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{
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unsigned short ctl, adv;
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/* Setup standard advertise */
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miiphy_read (devname, addr, PHY_ANAR, &adv);
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adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
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PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
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PHY_ANLPAR_10);
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miiphy_write (devname, addr, PHY_ANAR, adv);
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miiphy_read (devname, addr, PHY_1000BTCR, &adv);
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adv |= (0x0300);
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miiphy_write (devname, addr, PHY_1000BTCR, adv);
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/* Start/Restart aneg */
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miiphy_read (devname, addr, PHY_BMCR, &ctl);
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ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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miiphy_write (devname, addr, PHY_BMCR, ctl);
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return 0;
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}
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/***********************************************************/
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/* read a phy reg and return the value with a rc */
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/***********************************************************/
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unsigned int miiphy_getemac_offset (void)
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{
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#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
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unsigned long zmii;
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unsigned long eoffset;
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/* Need to find out which mdi port we're using */
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zmii = in32 (ZMII_FER);
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if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
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/* using port 0 */
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eoffset = 0;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
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/* using port 1 */
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eoffset = 0x100;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
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/* using port 2 */
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eoffset = 0x400;
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} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
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/* using port 3 */
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eoffset = 0x600;
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} else {
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/* None of the mdi ports are enabled! */
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/* enable port 0 */
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zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
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out32 (ZMII_FER, zmii);
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eoffset = 0;
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/* need to soft reset port 0 */
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zmii = in32 (EMAC_M0);
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zmii |= EMAC_M0_SRST;
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out32 (EMAC_M0, zmii);
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}
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return (eoffset);
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#else
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#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX)
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unsigned long rgmii;
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int devnum = 1;
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rgmii = in32(RGMII_FER);
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if (rgmii & (1 << (19 - devnum)))
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return 0x100;
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#endif
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return 0;
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#endif
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}
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int emac4xx_miiphy_read (char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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unsigned long emac_reg;
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emac_reg = miiphy_getemac_offset ();
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/* see if it is ready for 1000 nsec */
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i = 0;
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/* see if it is ready for sec */
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while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5) {
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#ifdef ET_DEBUG
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sta_reg = in32 (EMAC_STACR + emac_reg);
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printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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printf ("read err 1\n");
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#endif
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return -1;
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}
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i++;
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}
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sta_reg = reg; /* reg address */
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/* set clock (50Mhz) and read flags */
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
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#else
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sta_reg |= EMAC_STACR_READ;
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#endif
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#else
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sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
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#endif
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#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
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!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
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!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
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!defined(CONFIG_405EX)
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
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#endif
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sta_reg = sta_reg | (addr << 5); /* Phy address */
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sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
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out32 (EMAC_STACR + emac_reg, sta_reg);
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#ifdef ET_DEBUG
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printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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sta_reg = in32 (EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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i = 0;
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while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5) {
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return -1;
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}
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i++;
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sta_reg = in32 (EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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}
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if ((sta_reg & EMAC_STACR_PHYE) != 0) {
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return -1;
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}
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*value = *(short *) (&sta_reg);
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return 0;
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} /* phy_read */
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/***********************************************************/
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/* write a phy reg and return the value with a rc */
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/***********************************************************/
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int emac4xx_miiphy_write (char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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unsigned long sta_reg; /* STA scratch area */
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unsigned long i;
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unsigned long emac_reg;
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emac_reg = miiphy_getemac_offset ();
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/* see if it is ready for 1000 nsec */
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i = 0;
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while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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if (i > 5)
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return -1;
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udelay (7);
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i++;
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}
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sta_reg = 0;
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sta_reg = reg; /* reg address */
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/* set clock (50Mhz) and read flags */
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#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
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sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
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#else
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sta_reg |= EMAC_STACR_WRITE;
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#endif
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#else
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sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
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#endif
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#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
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!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
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!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
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!defined(CONFIG_405EX)
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
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#endif
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sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
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sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
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memcpy (&sta_reg, &value, 2); /* put in data */
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out32 (EMAC_STACR + emac_reg, sta_reg);
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/* wait for completion */
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i = 0;
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sta_reg = in32 (EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
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udelay (7);
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if (i > 5)
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return -1;
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i++;
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sta_reg = in32 (EMAC_STACR + emac_reg);
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#ifdef ET_DEBUG
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printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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}
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if ((sta_reg & EMAC_STACR_PHYE) != 0)
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return -1;
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return 0;
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} /* phy_write */
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