upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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346 lines
8.5 KiB
346 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <ns16550.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/sys_proto.h>
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#include <asm/arch-tegra/uart.h>
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#include <asm/arch-tegra/warmboot.h>
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#include <asm/arch-tegra/gpu.h>
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#include <asm/arch-tegra/usb.h>
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#include <asm/arch-tegra/xusb-padctl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pmu.h>
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#include <asm/arch/tegra.h>
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#ifdef CONFIG_TEGRA_CLOCK_SCALING
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#include <asm/arch/emc.h>
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#endif
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#include "emc.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
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U_BOOT_DEVICE(tegra_gpios) = {
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"gpio_tegra"
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};
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#endif
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__weak void pinmux_init(void) {}
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__weak void pin_mux_usb(void) {}
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__weak void pin_mux_spi(void) {}
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__weak void pin_mux_mmc(void) {}
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__weak void gpio_early_init_uart(void) {}
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__weak void pin_mux_display(void) {}
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__weak void start_cpu_fan(void) {}
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#if defined(CONFIG_TEGRA_NAND)
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__weak void pin_mux_nand(void)
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{
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funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
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}
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#endif
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/*
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* Routine: power_det_init
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* Description: turn off power detects
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*/
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static void power_det_init(void)
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{
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#if defined(CONFIG_TEGRA20)
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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/* turn off power detects */
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writel(0, &pmc->pmc_pwr_det_latch);
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writel(0, &pmc->pmc_pwr_det);
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#endif
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}
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__weak int tegra_board_id(void)
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{
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return -1;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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int board_id = tegra_board_id();
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printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
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if (board_id != -1)
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printf(", ID: %d\n", board_id);
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printf("\n");
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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__weak int tegra_lcd_pmic_init(int board_it)
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{
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return 0;
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}
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__weak int nvidia_board_init(void)
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{
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return 0;
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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__maybe_unused int err;
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__maybe_unused int board_id;
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/* Do clocks and UART first so that printf() works */
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clock_init();
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clock_verify();
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tegra_gpu_config();
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#ifdef CONFIG_TEGRA_SPI
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pin_mux_spi();
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#endif
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#ifdef CONFIG_MMC_SDHCI_TEGRA
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pin_mux_mmc();
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#endif
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/* Init is handled automatically in the driver-model case */
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#if defined(CONFIG_DM_VIDEO)
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pin_mux_display();
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#endif
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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power_det_init();
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#ifdef CONFIG_SYS_I2C_TEGRA
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# ifdef CONFIG_TEGRA_PMU
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if (pmu_set_nominal())
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debug("Failed to select nominal voltages\n");
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# ifdef CONFIG_TEGRA_CLOCK_SCALING
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err = board_emc_init();
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if (err)
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debug("Memory controller init failed: %d\n", err);
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# endif
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# endif /* CONFIG_TEGRA_PMU */
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#endif /* CONFIG_SYS_I2C_TEGRA */
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#ifdef CONFIG_USB_EHCI_TEGRA
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pin_mux_usb();
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#endif
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#if defined(CONFIG_DM_VIDEO)
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board_id = tegra_board_id();
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err = tegra_lcd_pmic_init(board_id);
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if (err) {
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debug("Failed to set up LCD PMIC\n");
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return err;
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}
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#endif
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#ifdef CONFIG_TEGRA_NAND
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pin_mux_nand();
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#endif
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tegra_xusb_padctl_init();
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#ifdef CONFIG_TEGRA_LP0
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/* save Sdram params to PMC 2, 4, and 24 for WB0 */
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warmboot_save_sdram_params();
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/* prepare the WB code to LP0 location */
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warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
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#endif
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return nvidia_board_init();
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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static void __gpio_early_init(void)
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{
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}
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void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
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int board_early_init_f(void)
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{
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if (!clock_early_init_done())
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clock_early_init();
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#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
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#define USBCMD_FS2 (1 << 15)
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{
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struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
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writel(USBCMD_FS2, &usbctlr->usb_cmd);
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}
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#endif
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/* Do any special system timer/TSC setup */
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (!tegra_cpu_is_non_secure())
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#endif
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arch_timer_init();
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pinmux_init();
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board_init_uart_f();
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/* Initialize periph GPIOs */
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gpio_early_init();
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gpio_early_init_uart();
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return 0;
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}
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#endif /* EARLY_INIT */
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int board_late_init(void)
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{
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (tegra_cpu_is_non_secure()) {
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printf("CPU is in NS mode\n");
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env_set("cpu_ns_mode", "1");
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} else {
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env_set("cpu_ns_mode", "");
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}
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#endif
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start_cpu_fan();
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return 0;
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}
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/*
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* In some SW environments, a memory carve-out exists to house a secure
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* monitor, a trusted OS, and/or various statically allocated media buffers.
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*
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* This carveout exists at the highest possible address that is within a
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* 32-bit physical address space.
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*
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* This function returns the total size of this carve-out. At present, the
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* returned value is hard-coded for simplicity. In the future, it may be
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* possible to determine the carve-out size:
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* - By querying some run-time information source, such as:
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* - A structure passed to U-Boot by earlier boot software.
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* - SoC registers.
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* - A call into the secure monitor.
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* - In the per-board U-Boot configuration header, based on knowledge of the
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* SW environment that U-Boot is being built for.
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*
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* For now, we support two configurations in U-Boot:
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* - 32-bit ports without any form of carve-out.
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* - 64 bit ports which are assumed to use a carve-out of a conservatively
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* hard-coded size.
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*/
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static ulong carveout_size(void)
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{
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#ifdef CONFIG_ARM64
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return SZ_512M;
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#else
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return 0;
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#endif
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}
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/*
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* Determine the amount of usable RAM below 4GiB, taking into account any
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* carve-out that may be assigned.
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*/
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static ulong usable_ram_size_below_4g(void)
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{
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ulong total_size_below_4g;
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ulong usable_size_below_4g;
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/*
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* The total size of RAM below 4GiB is the lesser address of:
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* (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
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* (b) The size RAM physically present in the system.
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*/
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if (gd->ram_size < SZ_2G)
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total_size_below_4g = gd->ram_size;
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else
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total_size_below_4g = SZ_2G;
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/* Calculate usable RAM by subtracting out any carve-out size */
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usable_size_below_4g = total_size_below_4g - carveout_size();
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return usable_size_below_4g;
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}
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/*
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* Represent all available RAM in either one or two banks.
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*
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* The first bank describes any usable RAM below 4GiB.
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* The second bank describes any RAM above 4GiB.
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*
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* This split is driven by the following requirements:
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* - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
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* property for memory below and above the 4GiB boundary. The layout of that
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* DT property is directly driven by the entries in the U-Boot bank array.
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* - The potential existence of a carve-out at the end of RAM below 4GiB can
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* only be represented using multiple banks.
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*
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* Explicitly removing the carve-out RAM from the bank entries makes the RAM
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* layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
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* command-line.
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*
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* This does mean that the DT U-Boot passes to the Linux kernel will not
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* include this RAM in /memory/reg at all. An alternative would be to include
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* all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
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* into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
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* Linux kernel will ever need to access any RAM in* the carve-out via a CPU
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* mapping, so either way is acceptable.
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*
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* On 32-bit systems, we never define a bank for RAM above 4GiB, since the
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* start address of that bank cannot be represented in the 32-bit .size
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* field.
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*/
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
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#ifdef CONFIG_PCI
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gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
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#endif
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#ifdef CONFIG_PHYS_64BIT
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if (gd->ram_size > SZ_2G) {
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gd->bd->bi_dram[1].start = 0x100000000;
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gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
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} else
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#endif
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{
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gd->bd->bi_dram[1].start = 0;
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gd->bd->bi_dram[1].size = 0;
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}
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return 0;
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}
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/*
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* Most hardware on 64-bit Tegra is still restricted to DMA to the lower
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* 32-bits of the physical address space. Cap the maximum usable RAM area
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* at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
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* boundary that most devices can address. Also, don't let U-Boot use any
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* carve-out, as mentioned above.
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*
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* This function is called before dram_init_banksize(), so we can't simply
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* return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
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}
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