upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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146 lines
3.8 KiB
146 lines
3.8 KiB
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* Chunhe Lan <Chunhe.Lan@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <malloc.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include <asm/fsl_serdes.h>
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#include <hwconfig.h>
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#include "../common/fman.h"
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#include "t4rdb.h"
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void fdt_fixup_board_enet(void *fdt)
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{
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FMAN_ENET)
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int i, interface;
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struct memac_mdio_info dtsec_mdio_info;
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struct memac_mdio_info tgec_mdio_info;
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struct mii_dev *dev;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1, srds_prtcl_s2;
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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tgec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the 10G MDIO bus */
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fm_memac_mdio_init(bis, &tgec_mdio_info);
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if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
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/* SGMII */
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fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
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fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
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fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
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} else {
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puts("Invalid SerDes1 protocol for T4240RDB\n");
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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interface = fm_info_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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#if (CONFIG_SYS_NUM_FMAN == 2)
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if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
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/* SGMII && XFI */
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fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
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fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
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fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
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fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
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fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
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} else {
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puts("Invalid SerDes2 protocol for T4240RDB\n");
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}
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for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
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interface = fm_info_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
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fm_info_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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#endif /* CONFIG_SYS_NUM_FMAN */
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cpu_eth_init(bis);
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#endif /* CONFIG_FMAN_ENET */
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return pci_eth_init(bis);
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}
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