upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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753 lines
26 KiB
753 lines
26 KiB
/*
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* Copy and modify from linux/drivers/serial/sh-sci.h
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*/
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#include <dm/platform_data/serial_sh.h>
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struct uart_port {
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unsigned long iobase; /* in/out[bwl] */
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unsigned char *membase; /* read/write[bwl] */
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unsigned long mapbase; /* for ioremap */
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enum sh_serial_type type; /* port type */
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enum sh_clk_mode clk_mode; /* clock mode */
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};
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#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
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#include <asm/regs306x.h>
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#endif
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#if defined(CONFIG_H8S2678)
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#include <asm/regs267x.h>
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#endif
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#if defined(CONFIG_CPU_SH7706) || \
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defined(CONFIG_CPU_SH7707) || \
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defined(CONFIG_CPU_SH7708) || \
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defined(CONFIG_CPU_SH7709)
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# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
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# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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#elif defined(CONFIG_CPU_SH7705)
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# define SCIF0 0xA4400000
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# define SCIF2 0xA4410000
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# define SCSMR_Ir 0xA44A0000
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# define IRDA_SCIF SCIF0
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# define SCPCR 0xA4000116
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# define SCPDR 0xA4000136
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/* Set the clock source,
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* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
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* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
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*/
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# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
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#elif defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define PORT_PTCR 0xA405011EUL
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# define PORT_PVCR 0xA4050122UL
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# define SCIF_ORER 0x0200 /* overrun error bit */
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#elif defined(CONFIG_SH_RTS7751R2D)
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# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7750R) || \
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defined(CONFIG_CPU_SH7750S) || \
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defined(CONFIG_CPU_SH7091) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R)
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# define SCSPTR1 0xffe0001c /* 8 bit SCI */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
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#elif defined(CONFIG_CPU_SH7760)
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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# define SCSCR_INIT(port) 0x3B
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#elif defined(CONFIG_CPU_SH7343)
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
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# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
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# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
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#elif defined(CONFIG_CPU_SH7722)
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# define PADR 0xA4050120
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# undef PSDR
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# define PSDR 0xA405013e
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# define PWDR 0xA4050166
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# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7723)
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# define SCSPTR0 0xa4050160
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# define SCSPTR1 0xa405013e
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# define SCSPTR2 0xa4050160
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# define SCSPTR3 0xa405013e
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# define SCSPTR4 0xa4050128
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# define SCSPTR5 0xa4050128
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7724)
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
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#elif defined(CONFIG_CPU_SH7734)
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# define SCSPTR0 0xFFE40020
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# define SCSPTR1 0xFFE41020
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# define SCSPTR2 0xFFE42020
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# define SCSPTR3 0xFFE43020
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# define SCSPTR4 0xFFE44020
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# define SCSPTR5 0xFFE45020
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
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# define SCIF_BASE_ADDR 0x01030000
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# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
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# define SCIF_PTR2_OFFS 0x0000020
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# define SCIF_LSR2_OFFS 0x0000024
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# define SCSPTR\
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((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
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# define SCLSR2\
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((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
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#elif defined(CONFIG_H8S2678)
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
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#elif defined(CONFIG_CPU_SH7757) || \
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defined(CONFIG_CPU_SH7752) || \
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defined(CONFIG_CPU_SH7753)
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# define SCSPTR0 0xfe4b0020
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# define SCSPTR1 0xfe4b0020
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# define SCSPTR2 0xfe4b0020
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# define SCIF_ORER 0x0001
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# define SCSCR_INIT(port) 0x38
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SH7763)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
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# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7770)
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# define SCSPTR0 0xff923020 /* 16 bit SCIF */
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# define SCSPTR1 0xff924020 /* 16 bit SCIF */
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# define SCSPTR2 0xff925020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
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#elif defined(CONFIG_CPU_SH7780)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#if defined(CONFIG_SH_SH2007)
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
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# define SCSCR_INIT(port) 0x38
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#else
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
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# define SCSCR_INIT(port) 0x3a
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#endif
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#elif defined(CONFIG_CPU_SH7785) || \
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defined(CONFIG_CPU_SH7786)
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# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
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# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
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# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
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# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
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# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
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# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7201) || \
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defined(CONFIG_CPU_SH7203) || \
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defined(CONFIG_CPU_SH7206) || \
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defined(CONFIG_CPU_SH7263) || \
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defined(CONFIG_CPU_SH7264)
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# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
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# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
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# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
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# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
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# if defined(CONFIG_CPU_SH7201)
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# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
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# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
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# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
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# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
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# endif
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7269)
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# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
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# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
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# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
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# define SCSPTR3 0xe8008820 /* 16 bit SCIF */
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# define SCSPTR4 0xe8009020 /* 16 bit SCIF */
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# define SCSPTR5 0xe8009820 /* 16 bit SCIF */
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# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
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# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SH7619)
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# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
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# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
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# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_CPU_SHX3)
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# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
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# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
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# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
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# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
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defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
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# define SCIF_ORER 0x0001
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# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
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#else
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# error CPU subtype not defined
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#endif
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/* SCSCR */
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#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
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#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
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#define SCI_CTRL_FLAGS_TE 0x20 /* all */
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#define SCI_CTRL_FLAGS_RE 0x10 /* all */
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#if defined(CONFIG_CPU_SH7750) || \
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defined(CONFIG_CPU_SH7091) || \
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defined(CONFIG_CPU_SH7750R) || \
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defined(CONFIG_CPU_SH7722) || \
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defined(CONFIG_CPU_SH7734) || \
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defined(CONFIG_CPU_SH7750S) || \
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defined(CONFIG_CPU_SH7751) || \
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defined(CONFIG_CPU_SH7751R) || \
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defined(CONFIG_CPU_SH7763) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785) || \
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defined(CONFIG_CPU_SH7786) || \
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defined(CONFIG_CPU_SHX3)
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#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
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#elif defined(CONFIG_CPU_SH7724)
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#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
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#else
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#define SCI_CTRL_FLAGS_REIE 0
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#endif
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/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
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/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
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/* SCxSR SCI */
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#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#if defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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# define SCIF_ORER 0x0200
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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#elif defined(CONFIG_CPU_SH7763)
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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/* SH7763 SCIF2 support */
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# define SCIF2_RFDC_MASK 0x001f
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# define SCIF2_TXROOM_MAX 16
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#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
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defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x003f
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#else
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# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x001f
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# define SCIF_TXROOM_MAX 16
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#endif
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#ifndef SCIF_ORER
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#define SCIF_ORER 0x0000
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#endif
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#define SCxSR_TEND(port)\
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(((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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#define SCxSR_ERRORS(port)\
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(((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
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#define SCxSR_RDxF(port)\
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(((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
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#define SCxSR_TDxE(port)\
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(((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
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#define SCxSR_FER(port)\
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(((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
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#define SCxSR_PER(port)\
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(((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
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#define SCxSR_BRK(port)\
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((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
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#define SCxSR_ORER(port)\
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(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
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#if defined(CONFIG_CPU_SH7705) || \
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defined(CONFIG_CPU_SH7720) || \
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defined(CONFIG_CPU_SH7721) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
|
|
defined(CONFIG_R8A7740)
|
|
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
|
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
|
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
|
# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
|
|
#else
|
|
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
|
|
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
|
|
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
|
|
# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
|
|
#endif
|
|
|
|
/* SCFCR */
|
|
#define SCFCR_RFRST 0x0002
|
|
#define SCFCR_TFRST 0x0004
|
|
#define SCFCR_TCRST 0x4000
|
|
#define SCFCR_MCE 0x0008
|
|
|
|
#define SCI_MAJOR 204
|
|
#define SCI_MINOR_START 8
|
|
|
|
/* Generic serial flags */
|
|
#define SCI_RX_THROTTLE 0x0000001
|
|
|
|
#define SCI_MAGIC 0xbabeface
|
|
|
|
/*
|
|
* Events are used to schedule things to happen at timer-interrupt
|
|
* time, instead of at rs interrupt time.
|
|
*/
|
|
#define SCI_EVENT_WRITE_WAKEUP 0
|
|
|
|
#define SCI_IN(size, offset)\
|
|
if ((size) == 8) {\
|
|
return readb(port->membase + (offset));\
|
|
} else {\
|
|
return readw(port->membase + (offset));\
|
|
}
|
|
#define SCI_OUT(size, offset, value)\
|
|
if ((size) == 8) {\
|
|
writeb(value, port->membase + (offset));\
|
|
} else if ((size) == 16) {\
|
|
writew(value, port->membase + (offset));\
|
|
}
|
|
|
|
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
|
|
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
|
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
|
|
SCI_IN(scif_size, scif_offset)\
|
|
} else { /* PORT_SCI or PORT_SCIFA */\
|
|
SCI_IN(sci_size, sci_offset);\
|
|
}\
|
|
}\
|
|
static inline void sci_##name##_out(struct uart_port *port,\
|
|
unsigned int value) {\
|
|
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
|
|
SCI_OUT(scif_size, scif_offset, value)\
|
|
} else { /* PORT_SCI or PORT_SCIFA */\
|
|
SCI_OUT(sci_size, sci_offset, value);\
|
|
}\
|
|
}
|
|
|
|
#ifdef CONFIG_H8300
|
|
/* h8300 don't have SCIF */
|
|
#define CPU_SCIF_FNS(name) \
|
|
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
|
return 0;\
|
|
}\
|
|
static inline void sci_##name##_out(struct uart_port *port,\
|
|
unsigned int value) {\
|
|
}
|
|
#else
|
|
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
|
|
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
|
SCI_IN(scif_size, scif_offset);\
|
|
}\
|
|
static inline void sci_##name##_out(struct uart_port *port,\
|
|
unsigned int value) {\
|
|
SCI_OUT(scif_size, scif_offset, value);\
|
|
}
|
|
#endif
|
|
|
|
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
|
|
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
|
|
SCI_IN(sci_size, sci_offset);\
|
|
}\
|
|
static inline void sci_##name##_out(struct uart_port *port,\
|
|
unsigned int value) {\
|
|
SCI_OUT(sci_size, sci_offset, value);\
|
|
}
|
|
|
|
#if defined(CONFIG_CPU_SH3) || \
|
|
defined(CONFIG_ARCH_SH7367) || \
|
|
defined(CONFIG_ARCH_SH7377) || \
|
|
defined(CONFIG_ARCH_SH7372) || \
|
|
defined(CONFIG_SH73A0) || \
|
|
defined(CONFIG_R8A7740)
|
|
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
|
|
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
|
sh4_sci_offset, sh4_sci_size, \
|
|
sh3_scif_offset, sh3_scif_size, \
|
|
sh4_scif_offset, sh4_scif_size, \
|
|
h8_sci_offset, h8_sci_size) \
|
|
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
|
|
sh4_scif_offset, sh4_scif_size)
|
|
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
|
#elif defined(CONFIG_CPU_SH7705) || \
|
|
defined(CONFIG_CPU_SH7720) || \
|
|
defined(CONFIG_CPU_SH7721) || \
|
|
defined(CONFIG_ARCH_SH7367) || \
|
|
defined(CONFIG_ARCH_SH7377) || \
|
|
defined(CONFIG_SH73A0)
|
|
#define SCIF_FNS(name, scif_offset, scif_size) \
|
|
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
|
#elif defined(CONFIG_ARCH_SH7372) || \
|
|
defined(CONFIG_R8A7740)
|
|
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
|
sh4_scifb_offset, sh4_scifb_size) \
|
|
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
|
sh4_scifb_offset, sh4_scifb_size)
|
|
#define SCIF_FNS(name, scif_offset, scif_size) \
|
|
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
|
#else
|
|
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
|
sh4_sci_offset, sh4_sci_size, \
|
|
sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size, \
|
|
h8_sci_offset, h8_sci_size) \
|
|
CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
|
sh3_scif_offset, sh3_scif_size)
|
|
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
|
|
#endif
|
|
#elif defined(__H8300H__) || defined(__H8300S__)
|
|
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
|
sh4_sci_offset, sh4_sci_size, \
|
|
sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size, \
|
|
h8_sci_offset, h8_sci_size) \
|
|
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
|
|
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIF_FNS(name)
|
|
#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
|
|
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
|
sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
|
|
sh4_scif_offset, sh4_scif_size)
|
|
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
|
#else
|
|
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
|
sh4_sci_offset, sh4_sci_size, \
|
|
sh3_scif_offset, sh3_scif_size,\
|
|
sh4_scif_offset, sh4_scif_size, \
|
|
h8_sci_offset, h8_sci_size) \
|
|
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
|
|
sh4_scif_offset, sh4_scif_size)
|
|
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
|
|
sh4_scif_offset, sh4_scif_size) \
|
|
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_SH7705) || \
|
|
defined(CONFIG_CPU_SH7720) || \
|
|
defined(CONFIG_CPU_SH7721) || \
|
|
defined(CONFIG_ARCH_SH7367) || \
|
|
defined(CONFIG_ARCH_SH7377) || \
|
|
defined(CONFIG_SH73A0)
|
|
|
|
SCIF_FNS(SCSMR, 0x00, 16)
|
|
SCIF_FNS(SCBRR, 0x04, 8)
|
|
SCIF_FNS(SCSCR, 0x08, 16)
|
|
SCIF_FNS(SCTDSR, 0x0c, 8)
|
|
SCIF_FNS(SCFER, 0x10, 16)
|
|
SCIF_FNS(SCxSR, 0x14, 16)
|
|
SCIF_FNS(SCFCR, 0x18, 16)
|
|
SCIF_FNS(SCFDR, 0x1c, 16)
|
|
SCIF_FNS(SCxTDR, 0x20, 8)
|
|
SCIF_FNS(SCxRDR, 0x24, 8)
|
|
SCIF_FNS(SCLSR, 0x00, 0)
|
|
SCIF_FNS(DL, 0x00, 0) /* dummy */
|
|
#elif defined(CONFIG_ARCH_SH7372) || \
|
|
defined(CONFIG_R8A7740)
|
|
SCIF_FNS(SCSMR, 0x00, 16)
|
|
SCIF_FNS(SCBRR, 0x04, 8)
|
|
SCIF_FNS(SCSCR, 0x08, 16)
|
|
SCIF_FNS(SCTDSR, 0x0c, 16)
|
|
SCIF_FNS(SCFER, 0x10, 16)
|
|
SCIF_FNS(SCxSR, 0x14, 16)
|
|
SCIF_FNS(SCFCR, 0x18, 16)
|
|
SCIF_FNS(SCFDR, 0x1c, 16)
|
|
SCIF_FNS(SCTFDR, 0x38, 16)
|
|
SCIF_FNS(SCRFDR, 0x3c, 16)
|
|
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
|
|
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
|
|
SCIF_FNS(SCLSR, 0x00, 0)
|
|
SCIF_FNS(DL, 0x00, 0) /* dummy */
|
|
#elif defined(CONFIG_CPU_SH7723) ||\
|
|
defined(CONFIG_CPU_SH7724)
|
|
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
|
|
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
|
|
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
|
|
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
|
|
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
|
|
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
|
|
SCIx_FNS(SCSPTR, 0, 0, 0, 0)
|
|
SCIF_FNS(SCTDSR, 0x0c, 8)
|
|
SCIF_FNS(SCFER, 0x10, 16)
|
|
SCIF_FNS(SCFCR, 0x18, 16)
|
|
SCIF_FNS(SCFDR, 0x1c, 16)
|
|
SCIF_FNS(SCLSR, 0x24, 16)
|
|
SCIF_FNS(DL, 0x00, 0) /* dummy */
|
|
#else
|
|
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
|
|
/* name off sz off sz off sz off sz off sz*/
|
|
SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
|
|
SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
|
|
SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
|
|
SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
|
|
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
|
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
|
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
|
#if defined(CONFIG_CPU_SH7760) || \
|
|
defined(CONFIG_CPU_SH7780) || \
|
|
defined(CONFIG_CPU_SH7785) || \
|
|
defined(CONFIG_CPU_SH7786)
|
|
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
|
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
|
#elif defined(CONFIG_CPU_SH7763)
|
|
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
|
|
SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
|
|
SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
|
|
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
|
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
|
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
|
#else
|
|
|
|
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
|
#if defined(CONFIG_CPU_SH7722)
|
|
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
|
|
#else
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
|
|
#endif
|
|
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
|
#endif
|
|
#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
|
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
|
SCIF_FNS(DL, 0, 0, 0x30, 16)
|
|
SCIF_FNS(CKS, 0, 0, 0x34, 16)
|
|
#else
|
|
SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
|
|
#endif
|
|
#endif
|
|
#define sci_in(port, reg) sci_##reg##_in(port)
|
|
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
|
|
|
|
/* H8/300 series SCI pins assignment */
|
|
#if defined(__H8300H__) || defined(__H8300S__)
|
|
static const struct __attribute__((packed)) {
|
|
int port; /* GPIO port no */
|
|
unsigned short rx, tx; /* GPIO bit no */
|
|
} h8300_sci_pins[] = {
|
|
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
|
{ /* SCI0 */
|
|
.port = H8300_GPIO_P9,
|
|
.rx = H8300_GPIO_B2,
|
|
.tx = H8300_GPIO_B0,
|
|
},
|
|
{ /* SCI1 */
|
|
.port = H8300_GPIO_P9,
|
|
.rx = H8300_GPIO_B3,
|
|
.tx = H8300_GPIO_B1,
|
|
},
|
|
{ /* SCI2 */
|
|
.port = H8300_GPIO_PB,
|
|
.rx = H8300_GPIO_B7,
|
|
.tx = H8300_GPIO_B6,
|
|
}
|
|
#elif defined(CONFIG_H8S2678)
|
|
{ /* SCI0 */
|
|
.port = H8300_GPIO_P3,
|
|
.rx = H8300_GPIO_B2,
|
|
.tx = H8300_GPIO_B0,
|
|
},
|
|
{ /* SCI1 */
|
|
.port = H8300_GPIO_P3,
|
|
.rx = H8300_GPIO_B3,
|
|
.tx = H8300_GPIO_B1,
|
|
},
|
|
{ /* SCI2 */
|
|
.port = H8300_GPIO_P5,
|
|
.rx = H8300_GPIO_B1,
|
|
.tx = H8300_GPIO_B0,
|
|
}
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_SH7706) || \
|
|
defined(CONFIG_CPU_SH7707) || \
|
|
defined(CONFIG_CPU_SH7708) || \
|
|
defined(CONFIG_CPU_SH7709)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
if (port->mapbase == 0xfffffe80)
|
|
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
|
|
return 1;
|
|
}
|
|
#elif defined(CONFIG_CPU_SH7750) || \
|
|
defined(CONFIG_CPU_SH7751) || \
|
|
defined(CONFIG_CPU_SH7751R) || \
|
|
defined(CONFIG_CPU_SH7750R) || \
|
|
defined(CONFIG_CPU_SH7750S) || \
|
|
defined(CONFIG_CPU_SH7091)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
if (port->mapbase == 0xffe00000)
|
|
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
|
return 1;
|
|
}
|
|
#elif defined(__H8300H__) || defined(__H8300S__)
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
int ch = (port->mapbase - SMR0) >> 3;
|
|
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
|
|
}
|
|
#else /* default case for non-SCI processors */
|
|
static inline int sci_rxd_in(struct uart_port *port)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Values for the BitRate Register (SCBRR)
|
|
*
|
|
* The values are actually divisors for a frequency which can
|
|
* be internal to the SH3 (14.7456MHz) or derived from an external
|
|
* clock source. This driver assumes the internal clock is used;
|
|
* to support using an external clock source, config options or
|
|
* possibly command-line options would need to be added.
|
|
*
|
|
* Also, to support speeds below 2400 (why?) the lower 2 bits of
|
|
* the SCSMR register would also need to be set to non-zero values.
|
|
*
|
|
* -- Greg Banks 27Feb2000
|
|
*
|
|
* Answer: The SCBRR register is only eight bits, and the value in
|
|
* it gets larger with lower baud rates. At around 2400 (depending on
|
|
* the peripherial module clock) you run out of bits. However the
|
|
* lower two bits of SCSMR allow the module clock to be divided down,
|
|
* scaling the value which is needed in SCBRR.
|
|
*
|
|
* -- Stuart Menefy - 23 May 2000
|
|
*
|
|
* I meant, why would anyone bother with bitrates below 2400.
|
|
*
|
|
* -- Greg Banks - 7Jul2000
|
|
*
|
|
* You "speedist"! How will I use my 110bps ASR-33 teletype with paper
|
|
* tape reader as a console!
|
|
*
|
|
* -- Mitch Davis - 15 Jul 2000
|
|
*/
|
|
|
|
#if (defined(CONFIG_CPU_SH7780) || \
|
|
defined(CONFIG_CPU_SH7785) || \
|
|
defined(CONFIG_CPU_SH7786)) && \
|
|
!defined(CONFIG_SH_SH2007)
|
|
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
|
#elif defined(CONFIG_CPU_SH7705) || \
|
|
defined(CONFIG_CPU_SH7720) || \
|
|
defined(CONFIG_CPU_SH7721) || \
|
|
defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) || \
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defined(CONFIG_SH73A0) || \
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defined(CONFIG_R8A7740)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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#elif defined(CONFIG_CPU_SH7723) ||\
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defined(CONFIG_CPU_SH7724)
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static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
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{
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if (port->type == PORT_SCIF)
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return (clk+16*bps)/(32*bps)-1;
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else
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|
return ((clk*2)+16*bps)/(16*bps)-1;
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|
}
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|
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
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|
#elif defined(__H8300H__) || defined(__H8300S__)
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|
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
|
|
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
|
|
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
|
|
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
|
|
#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
|
|
#else /* Generic SH */
|
|
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
|
|
#endif
|
|
|
|
#ifndef DL_VALUE
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|
#define DL_VALUE(bps, clk) 0
|
|
#endif
|
|
|