upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.5 KiB
59 lines
1.5 KiB
/*
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* Copyright (C) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/test.h>
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#include <dm/test.h>
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#include <linux/err.h>
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#include <test/ut.h>
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/* Test that we can find and adjust clocks */
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static int dm_test_clk_base(struct unit_test_state *uts)
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{
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struct udevice *clk;
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ulong rate;
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ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
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rate = clk_get_rate(clk);
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ut_asserteq(SANDBOX_CLK_RATE, rate);
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ut_asserteq(-EINVAL, clk_set_rate(clk, 0));
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ut_assertok(clk_set_rate(clk, rate * 2));
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ut_asserteq(SANDBOX_CLK_RATE * 2, clk_get_rate(clk));
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return 0;
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}
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DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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/* Test that peripheral clocks work as expected */
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static int dm_test_clk_periph(struct unit_test_state *uts)
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{
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struct udevice *clk;
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ulong rate;
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ut_assertok(uclass_get_device(UCLASS_CLK, 0, &clk));
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rate = clk_set_periph_rate(clk, PERIPH_ID_COUNT, 123);
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ut_asserteq(-EINVAL, rate);
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ut_asserteq(1, IS_ERR_VALUE(rate));
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rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 123);
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ut_asserteq(0, rate);
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ut_asserteq(123, clk_get_periph_rate(clk, PERIPH_ID_SPI));
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rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
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ut_asserteq(123, rate);
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rate = clk_set_periph_rate(clk, PERIPH_ID_I2C, 567);
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rate = clk_set_periph_rate(clk, PERIPH_ID_SPI, 1234);
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ut_asserteq(1234, rate);
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ut_asserteq(567, clk_get_periph_rate(clk, PERIPH_ID_I2C));
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return 0;
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}
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DM_TEST(dm_test_clk_periph, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
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