upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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83 lines
2.0 KiB
83 lines
2.0 KiB
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "clk-uniphier.h"
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#define UNIPHIER_MIO_CLK_SD_FIXED \
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UNIPHIER_CLK_RATE(128, 44444444), \
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UNIPHIER_CLK_RATE(129, 33333333), \
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UNIPHIER_CLK_RATE(130, 50000000), \
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UNIPHIER_CLK_RATE(131, 66666667), \
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UNIPHIER_CLK_RATE(132, 100000000), \
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UNIPHIER_CLK_RATE(133, 40000000), \
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UNIPHIER_CLK_RATE(134, 25000000), \
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UNIPHIER_CLK_RATE(135, 22222222)
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#define UNIPHIER_MIO_CLK_SD(_id, ch) \
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{ \
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.type = UNIPHIER_CLK_TYPE_MUX, \
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.id = (_id) + 32, \
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.data.mux = { \
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.parent_ids = { \
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128, \
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129, \
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130, \
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131, \
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132, \
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133, \
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134, \
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135, \
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}, \
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.num_parents = 8, \
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.reg = 0x30 + 0x200 * (ch), \
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.masks = { \
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0x00031000, \
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0x00031000, \
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0x00031000, \
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0x00031000, \
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0x00001300, \
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0x00001300, \
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0x00001300, \
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0x00001300, \
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}, \
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.vals = { \
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0x00000000, \
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0x00010000, \
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0x00020000, \
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0x00030000, \
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0x00001000, \
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0x00001100, \
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0x00001200, \
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0x00001300, \
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}, \
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}, \
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}, \
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UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
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#define UNIPHIER_MIO_CLK_USB2(id, ch) \
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UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 28)
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#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \
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UNIPHIER_CLK_GATE_SIMPLE((id), 0x20 + 0x200 * (ch), 29)
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#define UNIPHIER_MIO_CLK_DMAC(id) \
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UNIPHIER_CLK_GATE_SIMPLE((id), 0x20, 25)
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const struct uniphier_clk_data uniphier_mio_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
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UNIPHIER_MIO_CLK_SD(2, 2),
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UNIPHIER_MIO_CLK_DMAC(7),
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UNIPHIER_MIO_CLK_USB2(8, 0),
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UNIPHIER_MIO_CLK_USB2(9, 1),
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UNIPHIER_MIO_CLK_USB2(10, 2),
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UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
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UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
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UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
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{ /* sentinel */ }
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};
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