upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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531 lines
13 KiB
531 lines
13 KiB
/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <spd.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#ifdef CONFIG_SPD_EEPROM
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#if defined(CONFIG_DDR_ECC)
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extern void dma_init(void);
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extern uint dma_check(void);
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extern int dma_xfer(void *dest, uint count, void *src);
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#endif
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#ifndef CFG_READ_SPD
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#define CFG_READ_SPD i2c_read
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#endif
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/*
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* Convert picoseconds into clock cycles (rounding up if needed).
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*/
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int
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picos_to_clk(int picos)
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{
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int clks;
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clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
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if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
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clks++;
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}
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return clks;
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}
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unsigned int banksize(unsigned char row_dens)
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{
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return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
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}
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int read_spd(uint addr)
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{
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return ((int) addr);
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}
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#undef SPD_DEBUG
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#ifdef SPD_DEBUG
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static void spd_debug(spd_eeprom_t *spd)
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{
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printf ("\nDIMM type: %-18.18s\n", spd->mpart);
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printf ("SPD size: %d\n", spd->info_size);
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printf ("EEPROM size: %d\n", 1 << spd->chip_size);
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printf ("Memory type: %d\n", spd->mem_type);
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printf ("Row addr: %d\n", spd->nrow_addr);
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printf ("Column addr: %d\n", spd->ncol_addr);
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printf ("# of rows: %d\n", spd->nrows);
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printf ("Row density: %d\n", spd->row_dens);
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printf ("# of banks: %d\n", spd->nbanks);
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printf ("Data width: %d\n",
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256 * spd->dataw_msb + spd->dataw_lsb);
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printf ("Chip width: %d\n", spd->primw);
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printf ("Refresh rate: %02X\n", spd->refresh);
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printf ("CAS latencies: %02X\n", spd->cas_lat);
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printf ("Write latencies: %02X\n", spd->write_lat);
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printf ("tRP: %d\n", spd->trp);
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printf ("tRCD: %d\n", spd->trcd);
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printf ("\n");
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}
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#endif /* SPD_DEBUG */
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long int spd_sdram()
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ddr8349_t *ddr = &immap->ddr;
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volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
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spd_eeprom_t spd;
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unsigned tmp, tmp1;
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unsigned int memsize;
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unsigned int law_size;
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unsigned char caslat;
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unsigned int trfc, trfc_clk, trfc_low;
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CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
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#ifdef SPD_DEBUG
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spd_debug(&spd);
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#endif
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if (spd.nrows > 2) {
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puts("DDR:Only two chip selects are supported on ADS.\n");
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return 0;
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}
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if (spd.nrow_addr < 12
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|| spd.nrow_addr > 14
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|| spd.ncol_addr < 8
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|| spd.ncol_addr > 11) {
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puts("DDR:Row or Col number unsupported.\n");
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return 0;
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}
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ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
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ddr->cs_config[2] = ( 1 << 31
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| (spd.nrow_addr - 12) << 8
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| (spd.ncol_addr - 8) );
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debug("\n");
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debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
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debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
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if (spd.nrows == 2) {
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ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
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| ((banksize(spd.row_dens) >> 23) - 1) );
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ddr->cs_config[3] = ( 1<<31
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| (spd.nrow_addr-12) << 8
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| (spd.ncol_addr-8) );
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debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
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debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
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}
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if (spd.mem_type != 0x07) {
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puts("No DDR module found!\n");
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return 0;
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}
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/*
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* Figure out memory size in Megabytes.
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*/
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memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
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/*
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* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
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*/
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law_size = 19 + __ilog2(memsize);
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/*
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* Set up LAWBAR for all of DDR.
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*/
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ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
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debug("DDR:bar=0x%08x\n", ecm->bar);
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debug("DDR:ar=0x%08x\n", ecm->ar);
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/*
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* find the largest CAS
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*/
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if(spd.cas_lat & 0x40) {
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caslat = 7;
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} else if (spd.cas_lat & 0x20) {
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caslat = 6;
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} else if (spd.cas_lat & 0x10) {
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caslat = 5;
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} else if (spd.cas_lat & 0x08) {
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caslat = 4;
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} else if (spd.cas_lat & 0x04) {
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caslat = 3;
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} else if (spd.cas_lat & 0x02) {
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caslat = 2;
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} else if (spd.cas_lat & 0x01) {
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caslat = 1;
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} else {
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puts("DDR:no valid CAS Latency information.\n");
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return 0;
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}
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tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
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+ (spd.clk_cycle & 0x0f));
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debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
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tmp1 = get_bus_freq(0) / 1000000;
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if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
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/* 90~230 range, treated as DDR 200 */
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if (spd.clk_cycle3 == 0xa0)
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caslat -= 2;
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else if(spd.clk_cycle2 == 0xa0)
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caslat--;
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} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
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/* 230-280 range, treated as DDR 266 */
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if (spd.clk_cycle3 == 0x75)
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x75)
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caslat--;
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} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
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/* 280~350 range, treated as DDR 333 */
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if (spd.clk_cycle3 == 0x60)
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x60)
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caslat--;
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} else if (tmp1 < 90 || tmp1 >= 350) {
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/* DDR rate out-of-range */
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puts("DDR:platform frequency is not fit for DDR rate\n");
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return 0;
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}
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/*
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* note: caslat must also be programmed into ddr->sdram_mode
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* register.
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*
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* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
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* use conservative value here.
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*/
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trfc = spd.trfc * 1000; /* up to ps */
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trfc_clk = picos_to_clk(trfc);
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trfc_low = (trfc_clk - 8) & 0xf;
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ddr->timing_cfg_1 =
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(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
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((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
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((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
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((caslat & 0x07) << 16 ) |
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(trfc_low << 12 ) |
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( 0x300 ) |
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((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
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ddr->timing_cfg_2 = 0x00000800;
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debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
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debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
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/*
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* Only DDR I is supported
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* DDR I and II have different mode-register-set definition
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*/
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switch(caslat) {
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case 2:
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tmp = 0x50; /* 1.5 */
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break;
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case 3:
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tmp = 0x20; /* 2.0 */
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break;
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case 4:
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tmp = 0x60; /* 2.5 */
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break;
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case 5:
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tmp = 0x30; /* 3.0 */
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break;
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default:
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puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
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return 0;
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}
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#if defined (CONFIG_DDR_32BIT)
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/* set burst length to 8 for 32-bit data path */
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tmp |= 0x03;
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#else
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/* set burst length to 4 - default for 64-bit data path */
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tmp |= 0x02;
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#endif
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ddr->sdram_mode = tmp;
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debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
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switch(spd.refresh) {
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case 0x00:
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case 0x80:
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tmp = picos_to_clk(15625000);
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break;
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case 0x01:
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case 0x81:
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tmp = picos_to_clk(3900000);
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break;
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case 0x02:
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case 0x82:
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tmp = picos_to_clk(7800000);
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break;
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case 0x03:
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case 0x83:
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tmp = picos_to_clk(31300000);
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break;
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case 0x04:
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case 0x84:
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tmp = picos_to_clk(62500000);
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break;
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case 0x05:
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case 0x85:
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tmp = picos_to_clk(125000000);
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break;
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default:
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tmp = 0x512;
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break;
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}
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/*
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* Set BSTOPRE to 0x100 for page mode
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* If auto-charge is used, set BSTOPRE = 0
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*/
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ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
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debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
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/*
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* Is this an ECC DDR chip?
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*/
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#if defined(CONFIG_DDR_ECC)
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if (spd.config == 0x02) {
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/* disable error detection */
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ddr->err_disable = ~ECC_ERROR_ENABLE;
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/* set single bit error threshold to maximum value,
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* reset counter to zero */
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ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
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(0 << ECC_ERROR_MAN_SBEC_SHIFT);
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}
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debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
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debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
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#endif
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asm("sync;isync");
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udelay(500);
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/*
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* SS_EN=1,
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* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
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* clock cycle after address/command
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*/
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/*ddr->sdram_clk_cntl = 0x82000000;*/
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ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
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/*
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* Figure out the settings for the sdram_cfg register. Build up
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* the entire register in 'tmp' before writing since the write into
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* the register will actually enable the memory controller, and all
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* settings must be done before enabling.
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*
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* sdram_cfg[0] = 1 (ddr sdram logic enable)
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* sdram_cfg[1] = 1 (self-refresh-enable)
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* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
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*/
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tmp = 0xc2000000;
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#if defined (CONFIG_DDR_32BIT)
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/* in 32-Bit mode burst len is 8 beats */
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tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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/*
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* sdram_cfg[3] = RD_EN - registered DIMM enable
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* A value of 0x26 indicates micron registered DIMMS (micron.com)
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*/
|
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if (spd.mod_attr == 0x26) {
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tmp |= 0x10000000;
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}
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|
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#if defined(CONFIG_DDR_ECC)
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/*
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* If the user wanted ECC (enabled via sdram_cfg[2])
|
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*/
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if (spd.config == 0x02) {
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tmp |= SDRAM_CFG_ECC_EN;
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}
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#endif
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|
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#if defined(CONFIG_DDR_2T_TIMING)
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/*
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* Enable 2T timing by setting sdram_cfg[16].
|
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*/
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tmp |= SDRAM_CFG_2T_EN;
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#endif
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ddr->sdram_cfg = tmp;
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asm("sync;isync");
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udelay(500);
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debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
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return memsize; /*in MBytes*/
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|
}
|
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#endif /* CONFIG_SPD_EEPROM */
|
|
|
|
|
|
#if defined(CONFIG_DDR_ECC)
|
|
/*
|
|
* Use timebase counter, get_timer() is not availabe
|
|
* at this point of initialization yet.
|
|
*/
|
|
static __inline__ unsigned long get_tbms (void)
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|
{
|
|
unsigned long tbl;
|
|
unsigned long tbu1, tbu2;
|
|
unsigned long ms;
|
|
unsigned long long tmp;
|
|
|
|
ulong tbclk = get_tbclk();
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|
|
|
/* get the timebase ticks */
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|
do {
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|
asm volatile ("mftbu %0":"=r" (tbu1):);
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|
asm volatile ("mftb %0":"=r" (tbl):);
|
|
asm volatile ("mftbu %0":"=r" (tbu2):);
|
|
} while (tbu1 != tbu2);
|
|
|
|
/* convert ticks to ms */
|
|
tmp = (unsigned long long)(tbu1);
|
|
tmp = (tmp << 32);
|
|
tmp += (unsigned long long)(tbl);
|
|
ms = tmp/(tbclk/1000);
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|
|
|
return ms;
|
|
}
|
|
|
|
/*
|
|
* Initialize all of memory for ECC, then enable errors.
|
|
*/
|
|
//#define CONFIG_DDR_ECC_INIT_VIA_DMA
|
|
void ddr_enable_ecc(unsigned int dram_size)
|
|
{
|
|
uint *p;
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
|
|
volatile ddr8349_t *ddr = &immap->ddr;
|
|
unsigned long t_start, t_end;
|
|
#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
|
uint i;
|
|
#endif
|
|
|
|
debug("Initialize a Cachline in DRAM\n");
|
|
icache_enable();
|
|
|
|
#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
|
/* Initialise DMA for direct Transfers */
|
|
dma_init();
|
|
#endif
|
|
|
|
t_start = get_tbms();
|
|
|
|
#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
|
debug("DDR init: Cache flush method\n");
|
|
for (p = 0; p < (uint *)(dram_size); p++) {
|
|
if (((unsigned int)p & 0x1f) == 0) {
|
|
ppcDcbz((unsigned long) p);
|
|
}
|
|
|
|
/* write pattern to cache and flush */
|
|
*p = (unsigned int)0xdeadbeef;
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|
|
|
if (((unsigned int)p & 0x1c) == 0x1c) {
|
|
ppcDcbf((unsigned long) p);
|
|
}
|
|
}
|
|
#else
|
|
printf("DDR init: DMA method\n");
|
|
for (p = 0; p < (uint *)(8 * 1024); p++) {
|
|
/* zero one data cache line */
|
|
if (((unsigned int)p & 0x1f) == 0) {
|
|
ppcDcbz((unsigned long)p);
|
|
}
|
|
|
|
/* write pattern to it and flush */
|
|
*p = (unsigned int)0xdeadbeef;
|
|
|
|
if (((unsigned int)p & 0x1c) == 0x1c) {
|
|
ppcDcbf((unsigned long)p);
|
|
}
|
|
}
|
|
|
|
/* 8K */
|
|
dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
|
|
/* 16K */
|
|
dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
|
|
/* 32K */
|
|
dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
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/* 64K */
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dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
|
|
/* 128k */
|
|
dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
|
|
/* 256k */
|
|
dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
|
|
/* 512k */
|
|
dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
|
|
/* 1M */
|
|
dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
|
|
/* 2M */
|
|
dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
|
|
/* 4M */
|
|
dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
|
|
|
|
for (i = 1; i < dram_size / 0x800000; i++) {
|
|
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
|
|
}
|
|
#endif
|
|
|
|
t_end = get_tbms();
|
|
icache_disable();
|
|
|
|
debug("\nREADY!!\n");
|
|
debug("ddr init duration: %ld ms\n", t_end - t_start);
|
|
|
|
/* Clear All ECC Errors */
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MME;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MBE;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_SBE;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MSE;
|
|
|
|
/* Disable ECC-Interrupts */
|
|
ddr->err_int_en &= ECC_ERR_INT_DISABLE;
|
|
|
|
/* Enable errors for ECC */
|
|
ddr->err_disable &= ECC_ERROR_ENABLE;
|
|
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
}
|
|
#endif /* CONFIG_DDR_ECC */
|
|
|