upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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37 lines
681 B
37 lines
681 B
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#define CNT_CONTROL_BASE 0x60E00000
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#define CNTCR 0x000
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#define CNTCR_EN BIT(0)
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/* setup ARMv8 Generic Timer */
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int timer_init(void)
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{
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void __iomem *base;
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u32 tmp;
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base = ioremap(CNT_CONTROL_BASE, SZ_4K);
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/*
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* Note:
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* In a system that implements both Secure and Non-secure states,
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* this register is only writable in Secure state.
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*/
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tmp = readl(base + CNTCR);
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tmp |= CNTCR_EN;
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writel(tmp, base + CNTCR);
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iounmap(base);
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return 0;
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}
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