upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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164 lines
3.6 KiB
164 lines
3.6 KiB
#ifndef __S2MPS11__H__
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#define __S2MPS11__H__
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enum s2mps11_reg {
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S2MPS11_REG_ID = 0,
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S2MPS11_REG_INT1,
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S2MPS11_REG_INT2,
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S2MPS11_REG_INT3,
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S2MPS11_REG_INT1M,
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S2MPS11_REG_INT2M,
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S2MPS11_REG_INT3M,
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S2MPS11_REG_STATUS1,
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S2MPS11_REG_STATUS2,
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S2MPS11_REG_OFFSRC,
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S2MPS11_REG_PWRONSRC,
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S2MPS11_REG_RTC_CTRL,
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S2MPS11_REG_CTRL1,
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S2MPS11_REG_ETC_TEST,
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S2MPS11_REG_RSVD3,
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S2MPS11_REG_BU_CHG,
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S2MPS11_REG_RAMP,
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S2MPS11_REG_RAMP_BUCK,
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S2MPS11_REG_LDO1_8,
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S2MPS11_REG_LDO9_16,
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S2MPS11_REG_LDO17_24,
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S2MPS11_REG_LDO25_32,
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S2MPS11_REG_LDO33_38,
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S2MPS11_REG_LDO1_8_OVC,
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S2MPS11_REG_LDO9_16_OVC,
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S2MPS11_REG_LDO17_24_OVC,
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S2MPS11_REG_LDO25_32_OVC,
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S2MPS11_REG_LDO33_38_OVC,
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S2MPS11_REG_RESERVED1,
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S2MPS11_REG_RESERVED2,
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S2MPS11_REG_RESERVED3,
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S2MPS11_REG_RESERVED4,
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S2MPS11_REG_RESERVED5,
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S2MPS11_REG_RESERVED6,
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S2MPS11_REG_RESERVED7,
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S2MPS11_REG_RESERVED8,
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S2MPS11_REG_WDRSTEN_CTRL,
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S2MPS11_REG_B1CTRL1,
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S2MPS11_REG_B1CTRL2,
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S2MPS11_REG_B2CTRL1,
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S2MPS11_REG_B2CTRL2,
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S2MPS11_REG_B3CTRL1,
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S2MPS11_REG_B3CTRL2,
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S2MPS11_REG_B4CTRL1,
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S2MPS11_REG_B4CTRL2,
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S2MPS11_REG_B5CTRL1,
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S2MPS11_REG_BUCK5_SW,
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S2MPS11_REG_B5CTRL2,
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S2MPS11_REG_B5CTRL3,
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S2MPS11_REG_B5CTRL4,
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S2MPS11_REG_B5CTRL5,
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S2MPS11_REG_B6CTRL1,
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S2MPS11_REG_B6CTRL2,
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S2MPS11_REG_B7CTRL1,
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S2MPS11_REG_B7CTRL2,
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S2MPS11_REG_B8CTRL1,
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S2MPS11_REG_B8CTRL2,
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S2MPS11_REG_B9CTRL1,
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S2MPS11_REG_B9CTRL2,
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S2MPS11_REG_B10CTRL1,
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S2MPS11_REG_B10CTRL2,
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S2MPS11_REG_L1CTRL,
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S2MPS11_REG_L2CTRL,
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S2MPS11_REG_L3CTRL,
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S2MPS11_REG_L4CTRL,
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S2MPS11_REG_L5CTRL,
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S2MPS11_REG_L6CTRL,
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S2MPS11_REG_L7CTRL,
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S2MPS11_REG_L8CTRL,
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S2MPS11_REG_L9CTRL,
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S2MPS11_REG_L10CTRL,
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S2MPS11_REG_L11CTRL,
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S2MPS11_REG_L12CTRL,
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S2MPS11_REG_L13CTRL,
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S2MPS11_REG_L14CTRL,
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S2MPS11_REG_L15CTRL,
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S2MPS11_REG_L16CTRL,
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S2MPS11_REG_L17CTRL,
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S2MPS11_REG_L18CTRL,
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S2MPS11_REG_L19CTRL,
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S2MPS11_REG_L20CTRL,
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S2MPS11_REG_L21CTRL,
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S2MPS11_REG_L22CTRL,
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S2MPS11_REG_L23CTRL,
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S2MPS11_REG_L24CTRL,
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S2MPS11_REG_L25CTRL,
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S2MPS11_REG_L26CTRL,
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S2MPS11_REG_L27CTRL,
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S2MPS11_REG_L28CTRL,
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S2MPS11_REG_L29CTRL,
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S2MPS11_REG_L30CTRL,
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S2MPS11_REG_L31CTRL,
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S2MPS11_REG_L32CTRL,
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S2MPS11_REG_L33CTRL,
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S2MPS11_REG_L34CTRL,
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S2MPS11_REG_L35CTRL,
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S2MPS11_REG_L36CTRL,
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S2MPS11_REG_L37CTRL,
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S2MPS11_REG_L38CTRL,
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S2MPS11_REG_COUNT,
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};
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#define S2MPS11_LDO26_ENABLE 0xec
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#define S2MPS11_LDO_NUM 26
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#define S2MPS11_BUCK_NUM 10
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/* Driver name */
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#define S2MPS11_BUCK_DRIVER "s2mps11_buck"
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#define S2MPS11_OF_BUCK_PREFIX "BUCK"
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#define S2MPS11_LDO_DRIVER "s2mps11_ldo"
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#define S2MPS11_OF_LDO_PREFIX "LDO"
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/* BUCK */
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#define S2MPS11_BUCK_VOLT_MASK 0xff
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#define S2MPS11_BUCK9_VOLT_MASK 0x1f
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#define S2MPS11_BUCK_LSTEP 6250
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#define S2MPS11_BUCK_HSTEP 12500
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#define S2MPS11_BUCK9_STEP 25000
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#define S2MPS11_BUCK_UV_MIN 600000
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#define S2MPS11_BUCK_UV_HMIN 750000
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#define S2MPS11_BUCK9_UV_MIN 1400000
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#define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0
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#define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF
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#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC
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#define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F
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#define S2MPS11_BUCK_MODE_SHIFT 6
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#define S2MPS11_BUCK_MODE_MASK (0x3)
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#define S2MPS11_BUCK_MODE_OFF (0x0 << 6)
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#define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6)
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#define S2MPS11_BUCK_MODE_ON (0x3 << 6)
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/* LDO */
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#define S2MPS11_LDO_VOLT_MASK 0x3F
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#define S2MPS11_LDO_VOLT_MAX_HEX 0x3F
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#define S2MPS11_LDO_STEP 25000
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#define S2MPS11_LDO_UV_MIN 800000
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#define S2MPS11_LDO_MODE_MASK 0x3
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#define S2MPS11_LDO_MODE_SHIFT 6
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#define S2MPS11_LDO_MODE_OFF (0x0 << 6)
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#define S2MPS11_LDO_MODE_STANDBY (0x1 << 6)
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#define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6)
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#define S2MPS11_LDO_MODE_ON (0x3 << 6)
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enum {
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OP_OFF = 0,
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OP_LPM,
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OP_STANDBY,
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OP_STANDBY_LPM,
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OP_ON,
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};
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#endif
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