upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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360 lines
8.8 KiB
360 lines
8.8 KiB
/*
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* Copyright (C) 2004 IMMS gGmbH <www.imms.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* author(s): Thomas Elste, <info@elste.org>
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* (some parts derived from uCLinux Netarm Ethernet Driver)
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*/
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#include <common.h>
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#ifdef CONFIG_DRIVER_NETARMETH
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#include <command.h>
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#include <net.h>
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#include "netarm_eth.h"
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#include <asm/arch/netarm_registers.h>
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#if defined(CONFIG_CMD_NET)
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static int na_mii_poll_busy (void);
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static void na_get_mac_addr (void)
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{
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unsigned short p[3];
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char *m_addr;
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char ethaddr[20];
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m_addr = (char *) p;
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p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
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p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
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p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
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sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
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m_addr[0], m_addr[1],
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m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
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printf ("HW-MAC Address: %s\n", ethaddr);
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/* set env, todo: check if already an adress is set */
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setenv ("ethaddr", ethaddr);
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}
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static void na_mii_write (int reg, int value)
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{
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int mii_addr;
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/* Select register */
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mii_addr = CFG_ETH_PHY_ADDR + reg;
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SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
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/* Write value */
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SET_EADDR (NETARM_ETH_MII_WRITE, value);
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na_mii_poll_busy ();
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}
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static unsigned int na_mii_read (int reg)
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{
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int mii_addr, val;
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/* Select register */
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mii_addr = CFG_ETH_PHY_ADDR + reg;
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SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
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/* do one management cycle */
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SET_EADDR (NETARM_ETH_MII_CMD,
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GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
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na_mii_poll_busy ();
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/* Return read value */
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val = GET_EADDR (NETARM_ETH_MII_READ);
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return val;
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}
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static int na_mii_poll_busy (void)
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{
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/* arm simple, non interrupt dependent timer */
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reset_timer_masked ();
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while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
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if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
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return 1;
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}
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}
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printf ("na_mii_busy timeout\n");
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return (0);
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}
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static int na_mii_identify_phy (void)
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{
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int id_reg_a = 0;
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/* get phy id register */
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id_reg_a = na_mii_read (MII_PHY_ID);
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if (id_reg_a == 0x0043) {
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/* This must be an Enable or a Lucent LU3X31 PHY chip */
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return 1;
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} else if (id_reg_a == 0x0013) {
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/* it is an Intel LXT971A */
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return 1;
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}
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return (0);
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}
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static int na_mii_negotiate (void)
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{
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int i = 0;
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/* Enable auto-negotiation */
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na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
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/* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
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/* Restart auto-negotiation */
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na_mii_write (MII_PHY_CONTROL, 0x1200);
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/* status register is 0xffff after setting the autoneg restart bit */
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while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
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i++;
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}
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/* na_mii_read uses the timer already, so we can't use it again for
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timeout checking.
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Instead we just try some times.
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*/
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for (i = 0; i < 40000; i++) {
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if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
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return 0;
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}
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}
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/*
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printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
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*/
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return (1);
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}
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static unsigned int na_mii_check_speed (void)
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{
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unsigned int status;
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/* Read Status register */
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status = na_mii_read (MII_PHY_STATUS);
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/* Check link status. If 0, default to 100 Mbps. */
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if ((status & 0x0004) == 0) {
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printf ("*Warning* no link detected, set default speed to 100Mbs\n");
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return 1;
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} else {
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if ((na_mii_read (17) & 0x4000) != 0) {
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printf ("100Mbs link detected\n");
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return 1;
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} else {
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printf ("10Mbs link detected\n");
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return 0;
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}
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}
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return 0;
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}
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static int reset_eth (void)
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{
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int pt;
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na_get_mac_addr ();
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pt = na_mii_identify_phy ();
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/* reset the phy */
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na_mii_write (MII_PHY_CONTROL, 0x8000);
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reset_timer_masked ();
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while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) {
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if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
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break;
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}
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}
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if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY)
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printf ("phy reset timeout\n");
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/* set the PCS reg */
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SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
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NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
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na_mii_negotiate ();
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na_mii_check_speed ();
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/* Delay 10 millisecond. (Maybe this should be 1 second.) */
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udelay (10000);
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/* Turn receive on.
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Enable statistics register autozero on read.
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Do not insert MAC address on transmit.
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Do not enable special test modes. */
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SET_EADDR (NETARM_ETH_STL_CFG,
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(NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
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/* Set the inter-packet gap delay to 0.96us for MII.
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The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
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Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
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Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
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SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
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SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
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/* Add CRC to end of packets.
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Pad packets to minimum length of 64 bytes.
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Allow unlimited length transmit packets.
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Receive all broadcast packets.
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NOTE: Multicast addressing is NOT enabled here currently. */
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SET_EADDR (NETARM_ETH_MAC_CFG,
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(NETARM_ETH_MACC_CRCEN |
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NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
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SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
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/* enable fifos */
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SET_EADDR (NETARM_ETH_GEN_CTRL,
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(NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
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return (0);
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}
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extern int eth_init (bd_t * bd)
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{
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reset_eth ();
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return 0;
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}
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extern void eth_halt (void)
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{
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SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
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}
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/* Get a data block via Ethernet */
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extern int eth_rx (void)
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{
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int i;
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unsigned short rxlen;
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unsigned int *addr;
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unsigned int rxstatus, lastrxlen;
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char *pa;
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/* RXBR is 1, data block was received */
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if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
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return 0;
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/* get status register and the length of received block */
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rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
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rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
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if (rxlen == 0)
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return 0;
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/* clear RXBR to make fifo available */
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SET_EADDR (NETARM_ETH_GEN_STAT,
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GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
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/* clear TXBC to make fifo available */
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/* According to NETARM50 data manual you just have to clear
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RXBR but that has no effect. Only after clearing TXBC the
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Fifo becomes readable. */
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SET_EADDR (NETARM_ETH_GEN_STAT,
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GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
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addr = (unsigned int *) NetRxPackets[0];
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pa = (char *) NetRxPackets[0];
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/* read the fifo */
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for (i = 0; i < rxlen / 4; i++) {
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*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
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addr++;
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}
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if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
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/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
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lastrxlen =
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(GET_EADDR (NETARM_ETH_GEN_STAT) &
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NETARM_ETH_GST_RXFDB) >> 28;
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*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
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switch (lastrxlen) {
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case 1:
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*addr &= 0xff000000;
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break;
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case 2:
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*addr &= 0xffff0000;
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break;
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case 3:
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*addr &= 0xffffff00;
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break;
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}
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}
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/* Pass the packet up to the protocol layers. */
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NetReceive (NetRxPackets[0], rxlen);
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return rxlen;
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}
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/* Send a data block via Ethernet. */
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extern int eth_send (volatile void *packet, int length)
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{
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int i, length32;
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char *pa;
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unsigned int *pa32, lastp = 0, rest;
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pa = (char *) packet;
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pa32 = (unsigned int *) packet;
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length32 = length / 4;
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rest = length % 4;
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/* make sure there's no garbage in the last word */
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switch (rest) {
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case 0:
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lastp = pa32[length32];
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length32--;
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break;
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case 1:
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lastp = pa32[length32] & 0x000000ff;
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break;
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case 2:
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lastp = pa32[length32] & 0x0000ffff;
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break;
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case 3:
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lastp = pa32[length32] & 0x00ffffff;
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break;
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}
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/* write to the fifo */
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for (i = 0; i < length32; i++)
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SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
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/* the last word is written to an extra register, this
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starts the transmission */
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SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
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/* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
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went fine. But we can't use the timer for a timeout loop because
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of it is used already in upper layers. So we just try some times. */
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i = 0;
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while (i < 50000) {
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if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
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== NETARM_ETH_TXSTAT_TXOK)
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return 0;
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i++;
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}
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printf ("eth_send timeout\n");
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return 1;
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}
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#endif /* COMMANDS & CFG_NET */
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#endif /* CONFIG_DRIVER_NETARMETH */
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