upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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319 lines
7.4 KiB
319 lines
7.4 KiB
/***********************************************************************
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*
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* (C) Copyright 2004
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* DENX Software Engineering
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* Wolfgang Denk, wd@denx.de
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* All rights reserved.
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*
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* Simple 16550A serial driver
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*
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* Originally from linux source (drivers/char/ps2ser.c)
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*
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* Used by the PS/2 multiplexer driver (ps2mult.c)
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*
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***********************************************************************/
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#include <common.h>
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#ifdef CONFIG_PS2SERIAL
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#include <asm/io.h>
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#include <asm/atomic.h>
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#include <ps2mult.h>
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#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx)
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#include <ns16550.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* #define DEBUG */
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#define PS2SER_BAUD 57600
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#ifdef CONFIG_MPC5xxx
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#if CONFIG_PS2SERIAL == 1
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#define PSC_BASE MPC5XXX_PSC1
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#elif CONFIG_PS2SERIAL == 2
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#define PSC_BASE MPC5XXX_PSC2
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#elif CONFIG_PS2SERIAL == 3
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#define PSC_BASE MPC5XXX_PSC3
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#elif defined(CONFIG_MGT5100)
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#error CONFIG_PS2SERIAL must be in 1, 2 or 3
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#elif CONFIG_PS2SERIAL == 4
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#define PSC_BASE MPC5XXX_PSC4
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#elif CONFIG_PS2SERIAL == 5
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#define PSC_BASE MPC5XXX_PSC5
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#elif CONFIG_PS2SERIAL == 6
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#define PSC_BASE MPC5XXX_PSC6
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#else
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#error CONFIG_PS2SERIAL must be in 1 ... 6
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#endif
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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#if CONFIG_PS2SERIAL == 1
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#define COM_BASE (CFG_CCSRBAR+0x4500)
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#elif CONFIG_PS2SERIAL == 2
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#define COM_BASE (CFG_CCSRBAR+0x4600)
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#else
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#error CONFIG_PS2SERIAL must be in 1 ... 2
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#endif
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#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
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static int ps2ser_getc_hw(void);
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static void ps2ser_interrupt(void *dev_id);
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extern struct serial_state rs_table[]; /* in serial.c */
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#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
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static struct serial_state *state;
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#endif
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static u_char ps2buf[PS2BUF_SIZE];
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static atomic_t ps2buf_cnt;
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static int ps2buf_in_idx;
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static int ps2buf_out_idx;
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#ifdef CONFIG_MPC5xxx
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int ps2ser_init(void)
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{
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volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
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unsigned long baseclk;
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int div;
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/* reset PSC */
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psc->command = PSC_SEL_MODE_REG_1;
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/* select clock sources */
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#if defined(CONFIG_MGT5100)
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psc->psc_clock_select = 0xdd00;
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baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
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#elif defined(CONFIG_MPC5200)
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psc->psc_clock_select = 0;
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baseclk = (gd->ipb_clk + 16) / 32;
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#endif
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/* switch to UART mode */
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psc->sicr = 0;
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/* configure parity, bit length and so on */
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#if defined(CONFIG_MGT5100)
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psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
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#elif defined(CONFIG_MPC5200)
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psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
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#endif
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psc->mode = PSC_MODE_ONE_STOP;
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/* set up UART divisor */
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div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
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psc->ctur = (div >> 8) & 0xff;
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psc->ctlr = div & 0xff;
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/* disable all interrupts */
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psc->psc_imr = 0;
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/* reset and enable Rx/Tx */
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psc->command = PSC_RST_RX;
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psc->command = PSC_RST_TX;
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psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
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return (0);
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}
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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int ps2ser_init(void)
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{
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NS16550_t com_port = (NS16550_t)COM_BASE;
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com_port->ier = 0x00;
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com_port->lcr = LCR_BKSE | LCR_8N1;
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com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
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com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
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com_port->lcr = LCR_8N1;
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com_port->mcr = (MCR_DTR | MCR_RTS);
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com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
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return (0);
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}
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#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
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static inline unsigned int ps2ser_in(int offset)
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{
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return readb((unsigned long) state->iomem_base + offset);
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}
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static inline void ps2ser_out(int offset, int value)
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{
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writeb(value, (unsigned long) state->iomem_base + offset);
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}
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int ps2ser_init(void)
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{
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int quot;
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unsigned cval;
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state = rs_table + CONFIG_PS2SERIAL;
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quot = state->baud_base / PS2SER_BAUD;
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cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
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/* Set speed, enable interrupts, enable FIFO
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*/
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ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
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ps2ser_out(UART_DLL, quot & 0xff);
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ps2ser_out(UART_DLM, quot >> 8);
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ps2ser_out(UART_LCR, cval);
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ps2ser_out(UART_IER, UART_IER_RDI);
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ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
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ps2ser_out(UART_FCR,
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UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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/* If we read 0xff from the LSR, there is no UART here
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*/
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if (ps2ser_in(UART_LSR) == 0xff) {
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printf ("ps2ser.c: no UART found\n");
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return -1;
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}
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irq_install_handler(state->irq, ps2ser_interrupt, NULL);
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return 0;
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}
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#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
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void ps2ser_putc(int chr)
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{
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#ifdef CONFIG_MPC5xxx
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volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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NS16550_t com_port = (NS16550_t)COM_BASE;
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#endif
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#ifdef DEBUG
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printf(">>>> 0x%02x\n", chr);
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#endif
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#ifdef CONFIG_MPC5xxx
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while (!(psc->psc_status & PSC_SR_TXRDY));
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psc->psc_buffer_8 = chr;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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while ((com_port->lsr & LSR_THRE) == 0);
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com_port->thr = chr;
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#else
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while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
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ps2ser_out(UART_TX, chr);
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#endif
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}
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static int ps2ser_getc_hw(void)
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{
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#ifdef CONFIG_MPC5xxx
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volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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NS16550_t com_port = (NS16550_t)COM_BASE;
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#endif
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int res = -1;
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#ifdef CONFIG_MPC5xxx
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if (psc->psc_status & PSC_SR_RXRDY) {
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res = (psc->psc_buffer_8);
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}
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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if (com_port->lsr & LSR_DR) {
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res = com_port->rbr;
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}
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#else
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if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
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res = (ps2ser_in(UART_RX));
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}
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#endif
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return res;
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}
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int ps2ser_getc(void)
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{
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volatile int chr;
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int flags;
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#ifdef DEBUG
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printf("<< ");
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#endif
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flags = disable_interrupts();
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do {
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if (atomic_read(&ps2buf_cnt) != 0) {
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chr = ps2buf[ps2buf_out_idx++];
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ps2buf_out_idx &= (PS2BUF_SIZE - 1);
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atomic_dec(&ps2buf_cnt);
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} else {
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chr = ps2ser_getc_hw();
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}
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}
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while (chr < 0);
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if (flags) enable_interrupts();
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#ifdef DEBUG
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printf("0x%02x\n", chr);
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#endif
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return chr;
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}
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int ps2ser_check(void)
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{
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int flags;
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flags = disable_interrupts();
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ps2ser_interrupt(NULL);
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if (flags) enable_interrupts();
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return atomic_read(&ps2buf_cnt);
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}
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static void ps2ser_interrupt(void *dev_id)
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{
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#ifdef CONFIG_MPC5xxx
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volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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NS16550_t com_port = (NS16550_t)COM_BASE;
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#endif
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int chr;
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int status;
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do {
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chr = ps2ser_getc_hw();
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#ifdef CONFIG_MPC5xxx
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status = psc->psc_status;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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status = com_port->lsr;
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#else
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status = ps2ser_in(UART_IIR);
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#endif
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if (chr < 0) continue;
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if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
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ps2buf[ps2buf_in_idx++] = chr;
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ps2buf_in_idx &= (PS2BUF_SIZE - 1);
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atomic_inc(&ps2buf_cnt);
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} else {
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printf ("ps2ser.c: buffer overflow\n");
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}
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#ifdef CONFIG_MPC5xxx
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} while (status & PSC_SR_RXRDY);
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
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} while (status & LSR_DR);
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#else
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} while (status & UART_IIR_RDI);
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#endif
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if (atomic_read(&ps2buf_cnt)) {
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ps2mult_callback(atomic_read(&ps2buf_cnt));
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}
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}
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#endif /* CONFIG_PS2SERIAL */
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