upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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74 lines
2.1 KiB
74 lines
2.1 KiB
/*
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* (C) Copyright 2013
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* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MACH_FMC_H_
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#define _MACH_FMC_H_
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struct stm32_fmc_regs {
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u32 sdcr1; /* Control register 1 */
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u32 sdcr2; /* Control register 2 */
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u32 sdtr1; /* Timing register 1 */
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u32 sdtr2; /* Timing register 2 */
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u32 sdcmr; /* Mode register */
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u32 sdrtr; /* Refresh timing register */
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u32 sdsr; /* Status register */
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};
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/*
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* FMC registers base
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*/
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#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
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/* Control register SDCR */
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#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
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#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
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#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
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#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
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#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
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#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
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#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
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#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
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#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
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/* Timings register SDTR */
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#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
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#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
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#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
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#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
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#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
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#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
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#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
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#define FMC_SDCMR_NRFS_SHIFT 5
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#define FMC_SDCMR_MODE_NORMAL 0
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#define FMC_SDCMR_MODE_START_CLOCK 1
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#define FMC_SDCMR_MODE_PRECHARGE 2
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#define FMC_SDCMR_MODE_AUTOREFRESH 3
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#define FMC_SDCMR_MODE_WRITE_MODE 4
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#define FMC_SDCMR_MODE_SELFREFRESH 5
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#define FMC_SDCMR_MODE_POWERDOWN 6
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#define FMC_SDCMR_BANK_1 BIT(4)
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#define FMC_SDCMR_BANK_2 BIT(3)
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#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
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#define FMC_SDSR_BUSY BIT(5)
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#define FMC_BUSY_WAIT() do { \
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__asm__ __volatile__ ("dsb" : : : "memory"); \
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while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
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; \
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} while (0)
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#endif /* _MACH_FMC_H_ */
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