upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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878 lines
22 KiB
878 lines
22 KiB
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This source code is dual-licensed. You may use it under the terms of the
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* GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*/
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#include <common.h>
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#include <commproc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#include <ppc4xx.h>
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#ifdef CONFIG_SERIAL_MULTI
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#include <serial.h>
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#endif
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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#include <malloc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405EX) || defined(CONFIG_440)
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#if defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
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#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
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#else
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#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
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#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
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#endif
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
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#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
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#endif
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#if defined(CONFIG_440GP)
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#define CR0_MASK 0x3fff0000
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#define CR0_EXTCLK_ENA 0x00600000
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#define CR0_UDIV_POS 16
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#define UDIV_SUBTRACT 1
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#define UART0_SDR CPC0_CR0
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#define MFREG(a, d) d = mfdcr(a)
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#define MTREG(a, d) mtdcr(a, d)
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#else /* #if defined(CONFIG_440GP) */
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/* all other 440 PPC's access clock divider via sdr register */
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#define CR0_MASK 0xdfffffff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR SDR0_UART0
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#define UART1_SDR SDR0_UART1
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART2_SDR SDR0_UART2
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART3_SDR SDR0_UART3
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#endif
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#endif /* #if defined(CONFIG_440GP) */
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#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#elif defined(CONFIG_405EX)
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#define UART0_BASE 0xef600200
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#define UART1_BASE 0xef600300
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#define CR0_MASK 0x000000ff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR SDR0_UART0
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#define UART1_SDR SDR0_UART1
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#else /* CONFIG_405GP || CONFIG_405CR */
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define CR0_MASK 0x00001fff
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#define CR0_EXTCLK_ENA 0x000000c0
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#define CR0_UDIV_POS 1
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#define UDIV_MAX 32
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#endif
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/* using serial port 0 or 1 as U-Boot console ? */
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#if defined(CONFIG_UART1_CONSOLE)
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#define ACTING_UART0_BASE UART1_BASE
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#define ACTING_UART1_BASE UART0_BASE
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#else
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#define ACTING_UART0_BASE UART0_BASE
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#define ACTING_UART1_BASE UART1_BASE
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#endif
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#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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#error "External serial clock not supported on AMCC PPC405EP!"
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#endif
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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#define asyncLSRFramingError1 0x08
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#define asyncLSRBreakInterrupt1 0x10
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#define asyncLSRTxHoldEmpty1 0x20
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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/*-----------------------------------------------------------------------------+
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| Fifo
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+-----------------------------------------------------------------------------*/
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typedef struct {
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char *rx_buffer;
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ulong rx_put;
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ulong rx_get;
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} serial_buffer_t;
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volatile static serial_buffer_t buf_info;
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#endif
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static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
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{
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PPC4xx_SYS_INFO sys_info;
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u8 val;
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get_sys_info(&sys_info);
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available
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*/
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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#else
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gd->uart_clk = sys_info.freqUART / udiv;
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#endif
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out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
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out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
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out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
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out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in_8((u8 *)base + UART_LSR); /* clear line status */
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val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
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out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
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out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
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}
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#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
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!defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv)
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{
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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get_sys_info(&sysinfo);
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udiv = 32; /* Assume lowest possible serial clk */
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div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
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diff = 32; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (32) to minimize serial clock and constrain
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* search to umin.
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*/
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for (i = 32; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if (idiff == 0) {
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udiv = i;
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break; /* can't do better */
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} else if (idiff < diff) {
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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*pbdiv = div / udiv;
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}
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#elif defined(CONFIG_405EZ)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv)
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{
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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unsigned long plloutb;
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unsigned long cpr_pllc;
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u32 reg;
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/* check the pll feedback source */
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mfcpr(CPR0_PLLC, cpr_pllc);
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get_sys_info(&sysinfo);
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plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
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sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
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sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
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udiv = 256; /* Assume lowest possible serial clk */
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div = plloutb / (16 * baudrate); /* total divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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diff = 256; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (256) to minimize serial clock and constrain
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* search to umin.
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*/
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for (i = 256; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if (idiff == 0) {
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udiv = i;
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break; /* can't do better */
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} else if (idiff < diff) {
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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mfcpr(CPC0_PERD0, reg);
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reg &= ~0x0000ffff;
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reg |= ((udiv - 0) << 8) | (udiv - 0);
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mtcpr(CPC0_PERD0, reg);
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*pbdiv = div / udiv;
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}
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#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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#if defined(CONFIG_440)
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int serial_init_dev(unsigned long base)
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{
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unsigned long reg;
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unsigned long udiv;
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unsigned short bdiv;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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unsigned long tmp;
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#endif
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MFREG(UART0_SDR, reg);
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reg &= ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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reg |= CR0_EXTCLK_ENA;
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udiv = 1;
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tmp = gd->baudrate * 16;
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bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
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#else
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized"
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* values that are subject to the 1/2 opb clock constraint
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*/
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serial_divs (gd->baudrate, &udiv, &bdiv);
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#endif
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
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/*
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* Configure input clock to baudrate generator for all
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* available serial ports here
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*/
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MTREG(UART0_SDR, reg);
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#if defined(UART1_SDR)
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MTREG(UART1_SDR, reg);
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#endif
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#if defined(UART2_SDR)
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MTREG(UART2_SDR, reg);
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#endif
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#if defined(UART3_SDR)
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MTREG(UART3_SDR, reg);
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#endif
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serial_init_common(base, udiv, bdiv);
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return (0);
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}
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#else /* !defined(CONFIG_440) */
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int serial_init_dev (unsigned long base)
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{
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unsigned long reg;
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unsigned long tmp;
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unsigned long clk;
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unsigned long udiv;
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unsigned short bdiv;
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#ifdef CONFIG_405EX
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clk = tmp = 0;
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mfsdr(UART0_SDR, reg);
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reg &= ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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reg |= CR0_EXTCLK_ENA;
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udiv = 1;
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tmp = gd->baudrate * 16;
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bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
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#else
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serial_divs(gd->baudrate, &udiv, &bdiv);
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#endif
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
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/*
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* Configure input clock to baudrate generator for all
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* available serial ports here
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*/
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mtsdr(UART0_SDR, reg);
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#if defined(UART1_SDR)
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mtsdr(UART1_SDR, reg);
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#endif
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#elif defined(CONFIG_405EZ)
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serial_divs(gd->baudrate, &udiv, &bdiv);
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clk = tmp = reg = 0;
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#else
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#ifdef CONFIG_405EP
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reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
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clk = gd->cpu_clk;
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tmp = CONFIG_SYS_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
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reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
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mtdcr (CPC0_UCR, reg);
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#else /* CONFIG_405EP */
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reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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udiv = 1;
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reg |= CR0_EXTCLK_ENA;
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#else
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clk = gd->cpu_clk;
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#ifdef CONFIG_SYS_405_UART_ERRATA_59
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udiv = 31; /* Errata 59: stuck at 31 */
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#else
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tmp = CONFIG_SYS_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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#endif
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#endif
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (CPC0_CR0, reg);
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#endif /* CONFIG_405EP */
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tmp = gd->baudrate * udiv * 16;
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bdiv = (clk + tmp / 2) / tmp;
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#endif /* CONFIG_405EX */
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serial_init_common(base, udiv, bdiv);
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return (0);
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}
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#endif /* if defined(CONFIG_440) */
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void serial_setbrg_dev(unsigned long base)
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{
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serial_init_dev(base);
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}
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|
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void serial_putc_dev(unsigned long base, const char c)
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{
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int i;
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if (c == '\n')
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serial_putc_dev(base, '\r');
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|
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/* check THRE bit, wait for transmiter available */
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|
for (i = 1; i < 3500; i++) {
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if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
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break;
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udelay (100);
|
|
}
|
|
|
|
out_8((u8 *)base + UART_THR, c); /* put character out */
|
|
}
|
|
|
|
void serial_puts_dev (unsigned long base, const char *s)
|
|
{
|
|
while (*s)
|
|
serial_putc_dev (base, *s++);
|
|
}
|
|
|
|
int serial_getc_dev (unsigned long base)
|
|
{
|
|
unsigned char status = 0;
|
|
|
|
while (1) {
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
|
#endif /* CONFIG_HW_WATCHDOG */
|
|
|
|
status = in_8((u8 *)base + UART_LSR);
|
|
if ((status & asyncLSRDataReady1) != 0x0)
|
|
break;
|
|
|
|
if ((status & ( asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
out_8((u8 *)base + UART_LSR,
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
}
|
|
|
|
return (0x000000ff & (int) in_8((u8 *)base));
|
|
}
|
|
|
|
int serial_tstc_dev (unsigned long base)
|
|
{
|
|
unsigned char status;
|
|
|
|
status = in_8((u8 *)base + UART_LSR);
|
|
if ((status & asyncLSRDataReady1) != 0x0)
|
|
return (1);
|
|
|
|
if ((status & ( asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
out_8((u8 *)base + UART_LSR,
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
|
|
void serial_isr (void *arg)
|
|
{
|
|
int space;
|
|
int c;
|
|
const int rx_get = buf_info.rx_get;
|
|
int rx_put = buf_info.rx_put;
|
|
|
|
if (rx_get <= rx_put)
|
|
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
else
|
|
space = rx_get - rx_put;
|
|
|
|
while (serial_tstc_dev (ACTING_UART0_BASE)) {
|
|
c = serial_getc_dev (ACTING_UART0_BASE);
|
|
if (space) {
|
|
buf_info.rx_buffer[rx_put++] = c;
|
|
space--;
|
|
}
|
|
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
rx_put = 0;
|
|
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
|
|
/* Stop flow by setting RTS inactive */
|
|
out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
|
|
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
|
|
(0xFF ^ 0x02));
|
|
}
|
|
}
|
|
buf_info.rx_put = rx_put;
|
|
}
|
|
|
|
void serial_buffered_init (void)
|
|
{
|
|
serial_puts ("Switching to interrupt driven serial input mode.\n");
|
|
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
|
|
buf_info.rx_put = 0;
|
|
buf_info.rx_get = 0;
|
|
|
|
if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
|
|
serial_puts ("Check CTS signal present on serial port: OK.\n");
|
|
else
|
|
serial_puts ("WARNING: CTS signal not present on serial port.\n");
|
|
|
|
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
|
|
serial_isr /*interrupt_handler_t *handler */ ,
|
|
(void *) &buf_info /*void *arg */ );
|
|
|
|
/* Enable "RX Data Available" Interrupt on UART */
|
|
out_8(ACTING_UART0_BASE + UART_IER, 0x01);
|
|
/* Set DTR active */
|
|
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
|
|
/* Start flow by setting RTS active */
|
|
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
|
|
out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
|
|
}
|
|
|
|
void serial_buffered_putc (const char c)
|
|
{
|
|
/* Wait for CTS */
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
|
|
WATCHDOG_RESET ();
|
|
#else
|
|
while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
|
|
#endif
|
|
serial_putc (c);
|
|
}
|
|
|
|
void serial_buffered_puts (const char *s)
|
|
{
|
|
serial_puts (s);
|
|
}
|
|
|
|
int serial_buffered_getc (void)
|
|
{
|
|
int space;
|
|
int c;
|
|
int rx_get = buf_info.rx_get;
|
|
int rx_put;
|
|
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
while (rx_get == buf_info.rx_put)
|
|
WATCHDOG_RESET ();
|
|
#else
|
|
while (rx_get == buf_info.rx_put);
|
|
#endif
|
|
c = buf_info.rx_buffer[rx_get++];
|
|
if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
rx_get = 0;
|
|
buf_info.rx_get = rx_get;
|
|
|
|
rx_put = buf_info.rx_put;
|
|
if (rx_get <= rx_put)
|
|
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
else
|
|
space = rx_get - rx_put;
|
|
|
|
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
|
|
/* Start flow by setting RTS active */
|
|
out_8(ACTING_UART0_BASE + UART_MCR,
|
|
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
}
|
|
|
|
return c;
|
|
}
|
|
|
|
int serial_buffered_tstc (void)
|
|
{
|
|
return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
|
|
}
|
|
|
|
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
/*
|
|
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
|
|
number 0 or number 1
|
|
- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
|
|
configuration has been already done
|
|
- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
|
|
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
|
|
*/
|
|
#if (CONFIG_KGDB_SER_INDEX & 2)
|
|
void kgdb_serial_init (void)
|
|
{
|
|
u8 val;
|
|
u16 br_reg;
|
|
|
|
get_clocks ();
|
|
br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
|
|
5) / 10;
|
|
/*
|
|
* Init onboard 16550 UART
|
|
*/
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
|
|
val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
|
}
|
|
|
|
void putDebugChar (const char c)
|
|
{
|
|
if (c == '\n')
|
|
serial_putc ('\r');
|
|
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
|
|
|
|
/* check THRE bit, wait for transfer done */
|
|
while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
|
}
|
|
|
|
void putDebugStr (const char *s)
|
|
{
|
|
while (*s)
|
|
serial_putc (*s++);
|
|
}
|
|
|
|
int getDebugChar (void)
|
|
{
|
|
unsigned char status = 0;
|
|
|
|
while (1) {
|
|
status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
|
|
if ((status & asyncLSRDataReady1) != 0x0)
|
|
break;
|
|
|
|
if ((status & (asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
}
|
|
|
|
return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
|
|
}
|
|
|
|
void kgdb_interruptible (int yes)
|
|
{
|
|
return;
|
|
}
|
|
|
|
#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
|
|
|
|
void kgdb_serial_init (void)
|
|
{
|
|
serial_printf ("[on serial] ");
|
|
}
|
|
|
|
void putDebugChar (int c)
|
|
{
|
|
serial_putc (c);
|
|
}
|
|
|
|
void putDebugStr (const char *str)
|
|
{
|
|
serial_puts (str);
|
|
}
|
|
|
|
int getDebugChar (void)
|
|
{
|
|
return serial_getc ();
|
|
}
|
|
|
|
void kgdb_interruptible (int yes)
|
|
{
|
|
return;
|
|
}
|
|
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
|
|
#endif
|
|
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
int serial0_init(void)
|
|
{
|
|
return (serial_init_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_init(void)
|
|
{
|
|
return (serial_init_dev(UART1_BASE));
|
|
}
|
|
|
|
void serial0_setbrg (void)
|
|
{
|
|
serial_setbrg_dev(UART0_BASE);
|
|
}
|
|
|
|
void serial1_setbrg (void)
|
|
{
|
|
serial_setbrg_dev(UART1_BASE);
|
|
}
|
|
|
|
void serial0_putc(const char c)
|
|
{
|
|
serial_putc_dev(UART0_BASE,c);
|
|
}
|
|
|
|
void serial1_putc(const char c)
|
|
{
|
|
serial_putc_dev(UART1_BASE, c);
|
|
}
|
|
|
|
void serial0_puts(const char *s)
|
|
{
|
|
serial_puts_dev(UART0_BASE, s);
|
|
}
|
|
|
|
void serial1_puts(const char *s)
|
|
{
|
|
serial_puts_dev(UART1_BASE, s);
|
|
}
|
|
|
|
int serial0_getc(void)
|
|
{
|
|
return(serial_getc_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_getc(void)
|
|
{
|
|
return(serial_getc_dev(UART1_BASE));
|
|
}
|
|
|
|
int serial0_tstc(void)
|
|
{
|
|
return (serial_tstc_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_tstc(void)
|
|
{
|
|
return (serial_tstc_dev(UART1_BASE));
|
|
}
|
|
|
|
struct serial_device serial0_device =
|
|
{
|
|
"serial0",
|
|
"UART0",
|
|
serial0_init,
|
|
serial0_setbrg,
|
|
serial0_getc,
|
|
serial0_tstc,
|
|
serial0_putc,
|
|
serial0_puts,
|
|
};
|
|
|
|
struct serial_device serial1_device =
|
|
{
|
|
"serial1",
|
|
"UART1",
|
|
serial1_init,
|
|
serial1_setbrg,
|
|
serial1_getc,
|
|
serial1_tstc,
|
|
serial1_putc,
|
|
serial1_puts,
|
|
};
|
|
#else
|
|
/*
|
|
* Wrapper functions
|
|
*/
|
|
int serial_init(void)
|
|
{
|
|
return serial_init_dev(ACTING_UART0_BASE);
|
|
}
|
|
|
|
void serial_setbrg(void)
|
|
{
|
|
serial_setbrg_dev(ACTING_UART0_BASE);
|
|
}
|
|
|
|
void serial_putc(const char c)
|
|
{
|
|
serial_putc_dev(ACTING_UART0_BASE, c);
|
|
}
|
|
|
|
void serial_puts(const char *s)
|
|
{
|
|
serial_puts_dev(ACTING_UART0_BASE, s);
|
|
}
|
|
|
|
int serial_getc(void)
|
|
{
|
|
return serial_getc_dev(ACTING_UART0_BASE);
|
|
}
|
|
|
|
int serial_tstc(void)
|
|
{
|
|
return serial_tstc_dev(ACTING_UART0_BASE);
|
|
}
|
|
#endif /* CONFIG_SERIAL_MULTI */
|
|
|
|
#endif /* CONFIG_405GP || CONFIG_405CR */
|
|
|