upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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468 lines
12 KiB
468 lines
12 KiB
/*
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* DAVE Srl <www.dave-tech.it>
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*
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* (C) Copyright 2002-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include "sdram.h"
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#include "ecc.h"
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#ifdef CONFIG_SDRAM_BANK0
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#ifndef CONFIG_440
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#ifndef CONFIG_SYS_SDRAM_TABLE
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sdram_conf_t mb0cf[] = {
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{(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
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{(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
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{(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */
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{(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
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{(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
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};
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#else
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sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
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#endif
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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#ifdef CONFIG_SYS_SDRAM_CASL
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static ulong ns2clks(ulong ns)
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{
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ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10);
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return ((ns * 10) + bus_period_x_10) / bus_period_x_10;
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}
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#endif /* CONFIG_SYS_SDRAM_CASL */
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static ulong compute_sdtr1(ulong speed)
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{
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#ifdef CONFIG_SYS_SDRAM_CASL
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ulong tmp;
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ulong sdtr1 = 0;
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/* CASL */
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if (CONFIG_SYS_SDRAM_CASL < 2)
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sdtr1 |= (1 << SDRAM0_TR_CASL);
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else
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if (CONFIG_SYS_SDRAM_CASL > 4)
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sdtr1 |= (3 << SDRAM0_TR_CASL);
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else
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sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL);
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/* PTA */
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tmp = ns2clks(CONFIG_SYS_SDRAM_PTA);
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if ((tmp >= 2) && (tmp <= 4))
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sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA);
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else
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sdtr1 |= ((4-1) << SDRAM0_TR_PTA);
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/* CTP */
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tmp = ns2clks(CONFIG_SYS_SDRAM_CTP);
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if ((tmp >= 2) && (tmp <= 4))
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sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP);
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else
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sdtr1 |= ((4-1) << SDRAM0_TR_CTP);
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/* LDF */
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tmp = ns2clks(CONFIG_SYS_SDRAM_LDF);
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if ((tmp >= 2) && (tmp <= 4))
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sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF);
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else
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sdtr1 |= ((2-1) << SDRAM0_TR_LDF);
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/* RFTA */
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tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA);
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if ((tmp >= 4) && (tmp <= 10))
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sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA);
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else
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sdtr1 |= ((10-4) << SDRAM0_TR_RFTA);
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/* RCD */
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tmp = ns2clks(CONFIG_SYS_SDRAM_RCD);
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if ((tmp >= 2) && (tmp <= 4))
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sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD);
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else
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sdtr1 |= ((4-1) << SDRAM0_TR_RCD);
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return sdtr1;
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#else /* CONFIG_SYS_SDRAM_CASL */
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/*
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* If no values are configured in the board config file
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* use the default values, which seem to be ok for most
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* boards.
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*
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* REMARK:
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* For new board ports we strongly recommend to define the
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* correct values for the used SDRAM chips in your board
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* config file (see PPChameleonEVB.h)
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*/
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if (speed > 100000000) {
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/*
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* 133 MHz SDRAM
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*/
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return 0x01074015;
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} else {
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/*
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* default: 100 MHz SDRAM
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*/
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return 0x0086400d;
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}
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#endif /* CONFIG_SYS_SDRAM_CASL */
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}
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/* refresh is expressed in ms */
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static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
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{
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#ifdef CONFIG_SYS_SDRAM_CASL
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ulong tmp;
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tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000);
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tmp /= 1000000;
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return ((tmp & 0x00003FF8) << 16);
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#else /* CONFIG_SYS_SDRAM_CASL */
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if (speed > 100000000) {
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/*
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* 133 MHz SDRAM
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*/
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return 0x07f00000;
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} else {
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/*
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* default: 100 MHz SDRAM
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*/
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return 0x05f00000;
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}
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#endif /* CONFIG_SYS_SDRAM_CASL */
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}
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/*
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* Autodetect onboard SDRAM on 405 platforms
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*/
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phys_size_t initdram(int board_type)
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{
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ulong speed;
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ulong sdtr1;
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int i;
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/*
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* Determine SDRAM speed
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*/
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speed = get_bus_freq(0); /* parameter not used on ppc4xx */
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/*
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* sdtr1 (register SDRAM0_TR) must take into account timings listed
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* in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
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* account actual SDRAM size. So we can set up sdtr1 according to what
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* is specified in board configuration file while rtr dependds on SDRAM
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* size we are assuming before detection.
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*/
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sdtr1 = compute_sdtr1(speed);
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for (i=0; i<N_MB0CF; i++) {
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/*
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* Disable memory controller.
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*/
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mtsdram(SDRAM0_CFG, 0x00000000);
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/*
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* Set MB0CF for bank 0.
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*/
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mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
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mtsdram(SDRAM0_TR, sdtr1);
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mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram(SDRAM0_CFG, 0x80800000);
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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phys_size_t size = mb0cf[i].size;
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/*
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* OK, size detected. Enable second bank if
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* defined (assumes same type as bank 0)
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*/
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#ifdef CONFIG_SDRAM_BANK1
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mtsdram(SDRAM0_CFG, 0x00000000);
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mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
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mtsdram(SDRAM0_CFG, 0x80800000);
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udelay(10000);
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/*
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* Check if 2nd bank is really available.
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* If the size not equal to the size of the first
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* bank, then disable the 2nd bank completely.
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*/
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if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
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mb0cf[i].size) {
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mtsdram(SDRAM0_B1CR, 0);
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mtsdram(SDRAM0_CFG, 0);
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} else {
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/*
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* We have two identical banks, so the size
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* is twice the bank size
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*/
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size = 2 * size;
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}
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#endif
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/*
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* OK, size detected -> all done
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*/
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return size;
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}
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}
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return 0;
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}
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#else /* CONFIG_440 */
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/*
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* Define some default values. Those can be overwritten in the
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* board config file.
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*/
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#ifndef CONFIG_SYS_SDRAM_TABLE
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sdram_conf_t mb0cf[] = {
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{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
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{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */
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{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
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};
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#else
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sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
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#endif
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#ifndef CONFIG_SYS_SDRAM0_TR0
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#define CONFIG_SYS_SDRAM0_TR0 0x41094012
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#endif
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#ifndef CONFIG_SYS_SDRAM0_WDDCTR
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#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */
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#endif
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#ifndef CONFIG_SYS_SDRAM0_RTR
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#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */
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#endif
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#ifndef CONFIG_SYS_SDRAM0_CFG0
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#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
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#endif
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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#define NUM_TRIES 64
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#define NUM_READS 10
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static void sdram_tr1_set(int ram_address, int* tr1_value)
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{
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int i;
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int j, k;
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volatile unsigned int* ram_pointer = (unsigned int *)ram_address;
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int first_good = -1, last_bad = 0x1ff;
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unsigned long test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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/* go through all possible SDRAM0_TR1[RDCT] values */
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for (i=0; i<=0x1ff; i++) {
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/* set the current value for TR1 */
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mtsdram(SDRAM0_TR1, (0x80800800 | i));
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS)
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break;
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}
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/* we have a SDRAM0_TR1[RDCT] that is part of the window */
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if (j == NUM_TRIES) {
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if (first_good == -1)
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first_good = i; /* found beginning of window */
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} else { /* bad read */
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/* if we have not had a good read then don't care */
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if (first_good != -1) {
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/* first failure after a good read */
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last_bad = i-1;
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break;
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}
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}
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}
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/* return the current value for TR1 */
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*tr1_value = (first_good + last_bad) / 2;
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}
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/*
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* Autodetect onboard DDR SDRAM on 440 platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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phys_size_t initdram(int board_type)
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{
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int i;
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int tr1_bank1;
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#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
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defined(CONFIG_440GR) || defined(CONFIG_440SP)
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/*
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* Soft-reset SDRAM controller.
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*/
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mtsdr(SDR0_SRST, SDR0_SRST_DMC);
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mtsdr(SDR0_SRST, 0x00000000);
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#endif
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for (i=0; i<N_MB0CF; i++) {
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/*
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* Disable memory controller.
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*/
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mtsdram(SDRAM0_CFG0, 0x00000000);
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/*
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* Setup some default
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*/
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mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
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mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
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mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
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mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
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mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
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mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
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mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
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udelay(400); /* Delay 200 usecs (min) */
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/*
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* Enable the controller, then wait for DCEN to complete
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*/
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mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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phys_size_t size = mb0cf[i].size;
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/*
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* Optimize TR1 to current hardware environment
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*/
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sdram_tr1_set(0x00000000, &tr1_bank1);
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mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
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/*
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* OK, size detected. Enable second bank if
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* defined (assumes same type as bank 0)
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*/
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#ifdef CONFIG_SDRAM_BANK1
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mtsdram(SDRAM0_CFG0, 0);
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mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
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mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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/*
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* Check if 2nd bank is really available.
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* If the size not equal to the size of the first
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* bank, then disable the 2nd bank completely.
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*/
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if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
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!= mb0cf[i].size) {
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mtsdram(SDRAM0_CFG0, 0);
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mtsdram(SDRAM0_B1CR, 0);
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mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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} else {
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/*
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* We have two identical banks, so the size
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* is twice the bank size
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*/
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size = 2 * size;
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}
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#endif
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#ifdef CONFIG_SDRAM_ECC
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ecc_init(0, size);
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#endif
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/*
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* OK, size detected -> all done
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*/
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return size;
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}
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}
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return 0; /* nothing found ! */
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}
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#endif /* CONFIG_440 */
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#endif /* CONFIG_SDRAM_BANK0 */
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