upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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393 lines
13 KiB
393 lines
13 KiB
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _DDR3_INIT_H
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#define _DDR3_INIT_H
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#if defined(CONFIG_ARMADA_38X)
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#include "ddr3_a38x.h"
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#include "ddr3_a38x_mc_static.h"
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#include "ddr3_a38x_topology.h"
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#endif
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#include "ddr3_hws_hw_training.h"
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#include "ddr3_hws_sil_training.h"
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#include "ddr3_logging_def.h"
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#include "ddr3_training_hw_algo.h"
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#include "ddr3_training_ip.h"
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#include "ddr3_training_ip_centralization.h"
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#include "ddr3_training_ip_engine.h"
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#include "ddr3_training_ip_flow.h"
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#include "ddr3_training_ip_pbs.h"
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#include "ddr3_training_ip_prv_if.h"
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#include "ddr3_training_ip_static.h"
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#include "ddr3_training_leveling.h"
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#include "xor.h"
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/*
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* MV_DEBUG_INIT need to be defines, otherwise the output of the
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* DDR2 training code is not complete and misleading
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*/
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#define MV_DEBUG_INIT
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#ifdef MV_DEBUG_INIT
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#define DEBUG_INIT_S(s) puts(s)
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#define DEBUG_INIT_D(d, l) printf("%x", d)
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#define DEBUG_INIT_D_10(d, l) printf("%d", d)
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#else
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#define DEBUG_INIT_S(s)
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#define DEBUG_INIT_D(d, l)
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#define DEBUG_INIT_D_10(d, l)
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#endif
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#ifdef MV_DEBUG_INIT_FULL
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#define DEBUG_INIT_FULL_S(s) puts(s)
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#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
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#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
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#define DEBUG_WR_REG(reg, val) \
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{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#define DEBUG_RD_REG(reg, val) \
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{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#else
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#define DEBUG_INIT_FULL_S(s)
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#define DEBUG_INIT_FULL_D(d, l)
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#define DEBUG_INIT_FULL_D_10(d, l)
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#define DEBUG_WR_REG(reg, val)
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#define DEBUG_RD_REG(reg, val)
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#endif
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#define DEBUG_INIT_FULL_C(s, d, l) \
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{ DEBUG_INIT_FULL_S(s); \
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DEBUG_INIT_FULL_D(d, l); \
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DEBUG_INIT_FULL_S("\n"); }
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#define DEBUG_INIT_C(s, d, l) \
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{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
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/*
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* Debug (Enable/Disable modules) and Error report
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*/
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#ifdef BASIC_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS_RESULTS
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#endif
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#ifdef FULL_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS
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#define MV_DEBUG_PBS
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#define MV_DEBUG_DFS
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#define MV_DEBUG_MAIN_FULL
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#define MV_DEBUG_DFS_FULL
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#define MV_DEBUG_DQS_FULL
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#define MV_DEBUG_RL_FULL
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#define MV_DEBUG_WL_FULL
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#endif
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#if defined(CONFIG_ARMADA_38X)
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#include "ddr3_a38x.h"
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#include "ddr3_a38x_topology.h"
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#endif
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0x00) /* Operation succeeded */
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#define MV_FAIL (0x01) /* Operation failed */
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#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
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#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
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#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
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#define MV_BAD_PTR (0x05) /* Illegal pointer value */
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#define MV_BAD_SIZE (0x06) /* Illegal size */
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#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
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#define MV_SET_ERROR (0x08) /* Set operation failed */
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#define MV_GET_ERROR (0x09) /* Get operation failed */
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#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
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#define MV_NOT_FOUND (0x0b) /* Item not found */
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#define MV_NO_MORE (0x0c) /* No more items found */
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#define MV_NO_SUCH (0x0d) /* No such item */
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#define MV_TIMEOUT (0x0e) /* Time Out */
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#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
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#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
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#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
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#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
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#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
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#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
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#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
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#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
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#define MV_HW_ERROR (0x17) /* Hardware error */
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#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
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#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
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#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
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#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
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#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
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#define MV_NOT_STARTED (0x1d) /* Not started yet */
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#define MV_BUSY (0x1e) /* Item is busy. */
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#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
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#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
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#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
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#define MV_WRITE_PROTECT (0x22) /* Write protected */
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#define MV_INVALID (int)(-1)
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/* For checking function return values */
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#define CHECK_STATUS(orig_func) \
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{ \
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int status; \
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status = orig_func; \
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if (MV_OK != status) \
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return status; \
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}
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enum log_level {
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MV_LOG_LEVEL_0,
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MV_LOG_LEVEL_1,
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MV_LOG_LEVEL_2,
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MV_LOG_LEVEL_3
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};
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/* Globals */
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extern u8 debug_training;
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extern u8 is_reg_dump;
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extern u8 generic_init_controller;
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extern u32 freq_val[];
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extern u32 is_pll_old;
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extern struct cl_val_per_freq cas_latency_table[];
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extern struct pattern_info pattern_table[];
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extern struct cl_val_per_freq cas_write_latency_table[];
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extern u8 debug_training;
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extern u8 debug_centralization, debug_training_ip, debug_training_bist,
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debug_pbs, debug_training_static, debug_leveling;
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extern u32 pipe_multicast_mask;
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extern struct hws_tip_config_func_db config_func_info[];
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extern u8 cs_mask_reg[];
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extern u8 twr_mask_table[];
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extern u8 cl_mask_table[];
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extern u8 cwl_mask_table[];
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extern u16 rfc_table[];
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extern u32 speed_bin_table_t_rc[];
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extern u32 speed_bin_table_t_rcd_t_rp[];
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extern u32 ck_delay, ck_delay_16;
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extern u32 g_zpri_data;
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extern u32 g_znri_data;
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extern u32 g_zpri_ctrl;
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extern u32 g_znri_ctrl;
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extern u32 g_zpodt_data;
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extern u32 g_znodt_data;
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extern u32 g_zpodt_ctrl;
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extern u32 g_znodt_ctrl;
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extern u32 g_dic;
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extern u32 g_odt_config;
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extern u32 g_rtt_nom;
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extern u8 debug_training_access;
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extern u8 debug_training_a38x;
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extern u32 first_active_if;
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extern enum hws_ddr_freq init_freq;
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extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
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extern u32 mask_tune_func;
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extern u32 rl_version;
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extern int rl_mid_freq_wa;
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extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
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extern enum hws_ddr_freq medium_freq;
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extern u32 ck_delay, ck_delay_16;
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extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
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extern u32 first_active_if;
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extern u32 mask_tune_func;
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extern u32 freq_val[];
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extern enum hws_ddr_freq init_freq;
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extern enum hws_ddr_freq low_freq;
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extern enum hws_ddr_freq medium_freq;
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extern u8 generic_init_controller;
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extern enum auto_tune_stage training_stage;
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extern u32 is_pll_before_init;
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extern u32 is_adll_calib_before_init;
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extern u32 is_dfs_in_init;
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extern int wl_debug_delay;
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extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
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extern u32 p_finger;
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extern u32 n_finger;
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extern u32 freq_val[DDR_FREQ_LIMIT];
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extern u32 start_pattern, end_pattern;
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extern u32 phy_reg0_val;
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extern u32 phy_reg1_val;
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extern u32 phy_reg2_val;
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extern u32 phy_reg3_val;
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extern enum hws_pattern sweep_pattern;
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extern enum hws_pattern pbs_pattern;
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extern u8 is_rzq6;
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extern u32 znri_data_phy_val;
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extern u32 zpri_data_phy_val;
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extern u32 znri_ctrl_phy_val;
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extern u32 zpri_ctrl_phy_val;
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extern u8 debug_training_access;
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extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
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n_finger_end, p_finger_step, n_finger_step;
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extern u32 mode2_t;
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extern u32 xsb_validate_type;
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extern u32 xsb_validation_base_address;
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extern u32 odt_additional;
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extern u32 debug_mode;
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extern u32 delay_enable;
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extern u32 ca_delay;
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extern u32 debug_dunit;
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extern u32 clamp_tbl[];
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extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
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extern u32 start_pattern, end_pattern;
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extern u32 maxt_poll_tries;
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extern u32 is_bist_reset_bit;
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extern u8 debug_training_bist;
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extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
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extern u32 debug_mode;
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extern u32 effective_cs;
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extern int ddr3_tip_centr_skip_min_win_check;
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extern u32 *dq_map_table;
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extern enum auto_tune_stage training_stage;
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extern u8 debug_centralization;
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extern u32 delay_enable;
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extern u32 start_pattern, end_pattern;
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extern u32 freq_val[DDR_FREQ_LIMIT];
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extern u8 debug_training_hw_alg;
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extern enum auto_tune_stage training_stage;
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extern u8 debug_training_ip;
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extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
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extern enum auto_tune_stage training_stage;
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extern u32 effective_cs;
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extern u8 debug_leveling;
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extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
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extern enum auto_tune_stage training_stage;
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extern u32 rl_version;
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extern struct cl_val_per_freq cas_latency_table[];
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extern u32 start_xsb_offset;
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extern u32 debug_mode;
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extern u32 odt_config;
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extern u32 effective_cs;
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extern u32 phy_reg1_val;
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extern u8 debug_pbs;
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extern u32 effective_cs;
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extern u16 mask_results_dq_reg_map[];
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extern enum hws_ddr_freq medium_freq;
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extern u32 freq_val[];
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extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
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extern enum auto_tune_stage training_stage;
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extern u32 debug_mode;
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extern u32 *dq_map_table;
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extern u32 vref;
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extern struct cl_val_per_freq cas_latency_table[];
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extern u32 target_freq;
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extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
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extern u32 clamp_tbl[];
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extern u32 init_freq;
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/* list of allowed frequency listed in order of enum hws_ddr_freq */
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extern u32 freq_val[];
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extern u8 debug_training_static;
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extern u32 first_active_if;
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/* Prototypes */
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int ddr3_tip_enable_init_sequence(u32 dev_num);
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int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
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int ddr3_hws_hw_training(void);
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int ddr3_silicon_pre_init(void);
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int ddr3_silicon_post_init(void);
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int ddr3_post_run_alg(void);
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int ddr3_if_ecc_enabled(void);
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void ddr3_new_tip_ecc_scrub(void);
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void ddr3_print_version(void);
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void ddr3_new_tip_dlb_config(void);
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struct hws_topology_map *ddr3_get_topology_map(void);
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int ddr3_if_ecc_enabled(void);
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int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
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int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
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int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
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int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
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struct hws_tip_freq_config_info
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*freq_config_info);
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int ddr3_a38x_update_topology_map(u32 dev_num,
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struct hws_topology_map *topology_map);
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int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
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int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
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int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 *data, u32 mask);
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int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
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u32 if_id, u32 reg_addr, u32 data, u32 mask);
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int ddr3_tip_a38x_get_device_info(u8 dev_num,
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struct ddr3_device_info *info_ptr);
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int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
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int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
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int ddr3_tip_restore_dunit_regs(u32 dev_num);
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void print_topology(struct hws_topology_map *topology_db);
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u32 mv_board_id_get(void);
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int ddr3_load_topology_map(void);
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int ddr3_tip_init_specific_reg_config(u32 dev_num,
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struct reg_data *reg_config_arr);
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u32 ddr3_tip_get_init_freq(void);
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void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
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int ddr3_tip_tune_training_params(u32 dev_num,
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struct tune_train_params *params);
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void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
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int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
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void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
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u32 ddr3_get_device_width(u32 cs);
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u32 mv_board_id_index_get(u32 board_id);
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u32 mv_board_id_get(void);
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u32 ddr3_get_bus_width(void);
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void ddr3_set_log_level(u32 n_log_level);
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int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
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int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
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int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
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int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
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int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
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struct trip_delay_element *table_ptr,
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int is_wl, u32 *round_trip_delay_arr);
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u32 hws_ddr3_tip_max_cs_get(void);
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/*
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* Accessor functions for the registers
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*/
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static inline void reg_write(u32 addr, u32 val)
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{
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writel(val, INTER_REGS_BASE + addr);
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}
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static inline u32 reg_read(u32 addr)
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{
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return readl(INTER_REGS_BASE + addr);
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}
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static inline void reg_bit_set(u32 addr, u32 mask)
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{
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setbits_le32(INTER_REGS_BASE + addr, mask);
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}
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static inline void reg_bit_clr(u32 addr, u32 mask)
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{
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clrbits_le32(INTER_REGS_BASE + addr, mask);
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}
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#endif /* _DDR3_INIT_H */
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