upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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105 lines
2.7 KiB
105 lines
2.7 KiB
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/arch/kirkwood.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08))
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#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
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/*
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* kw_sdram_bar - reads SDRAM Base Address Register
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*/
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u32 kw_sdram_bar(enum memory_bank bank)
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{
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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if ((!enable) || (bank > BANK3))
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return 0;
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result = readl(KW_REG_CPUCS_WIN_BAR(bank));
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return result;
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}
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/*
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* kw_sdram_bs - reads SDRAM Bank size
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*/
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u32 kw_sdram_bs(enum memory_bank bank)
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{
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u32 result = 0;
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u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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if ((!enable) || (bank > BANK3))
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return 0;
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result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
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result += 0x01000000;
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return result;
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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int dram_init(void)
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{
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int i;
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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* If the gap is found, ram_size will be reported for
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* consecutive memory only
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*/
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if (gd->bd->bi_dram[i].start != gd->ram_size)
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break;
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gd->ram_size += gd->bd->bi_dram[i].size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* If above loop terminated prematurely, we need to set
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* remaining banks' start address & size as 0. Otherwise other
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* u-boot functions and Linux kernel gets wrong values which
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* could result in crash */
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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return 0;
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}
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/*
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* If this function is not defined here,
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* board.c alters dram bank zero configuration defined above.
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*/
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void dram_init_banksize(void)
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{
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dram_init();
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}
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#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
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