upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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147 lines
6.0 KiB
147 lines
6.0 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _TMU_CSR_H_
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#define _TMU_CSR_H_
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#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
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#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
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#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
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#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
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#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
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#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
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#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
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#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
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#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
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#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
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#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
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#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
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#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
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#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
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#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
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#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
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#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
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#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
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#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
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#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
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#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
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#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
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#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
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#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
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#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
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#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
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#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
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#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
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#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
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#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
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#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
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#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
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#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
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#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
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#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
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#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
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#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
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#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
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#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
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#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
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#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
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#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
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#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
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#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
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#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
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#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
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/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
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* This is a global Enable for all schedulers in PHY0
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*/
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#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
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#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
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#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
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#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
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#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
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#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
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#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
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#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
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#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
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#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
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#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
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/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
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* memory Write [27:24] Byte Enables of the Internal memory access [23:0]
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* Address of the internal memory. This address is used to access both the
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* PM and DM of all the PE's
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*/
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#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
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/* Internal Memory Access Write Data */
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#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
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/* Internal Memory Access Read Data. The commands are blocked at the
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* mem_access only
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*/
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#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
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/* [31:0] PHY0 in queue address (must be initialized with one of the
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* xxx_INQ_PKTPTR cbus addresses)
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*/
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#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
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/* [31:0] PHY1 in queue address (must be initialized with one of the
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* xxx_INQ_PKTPTR cbus addresses)
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*/
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#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
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/* [31:0] PHY3 in queue address (must be initialized with one of the
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* xxx_INQ_PKTPTR cbus addresses)
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*/
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#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
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#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
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#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
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#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
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#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
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#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
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/* [31:0] PHY4 in queue address (must be initialized with one of the
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* xxx_INQ_PKTPTR cbus addresses)
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*/
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#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
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/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
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* is a global Enable for all schedulers in PHY1
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*/
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#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
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/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
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* is a global Enable for all schedulers in PHY3
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*/
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#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
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#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
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/* [31:0] PHY5 in queue address (must be initialized with one of the
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* xxx_INQ_PKTPTR cbus addresses)
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*/
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#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
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#define TMU_AXI_CTRL (TMU_CSR_BASE_ADDR + 0x17c)
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#define SW_RESET BIT(0) /* Global software reset */
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#define INQ_RESET BIT(2)
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#define TEQ_RESET BIT(3)
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#define TDQ_RESET BIT(4)
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#define PE_RESET BIT(5)
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#define MEM_INIT BIT(6)
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#define MEM_INIT_DONE BIT(7)
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#define LLM_INIT BIT(8)
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#define LLM_INIT_DONE BIT(9)
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#define ECC_MEM_INIT_DONE BIT(10)
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struct tmu_cfg {
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u32 llm_base_addr;
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u32 llm_queue_len;
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};
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/* Not HW related for pfe_ctrl/pfe common defines */
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#define DEFAULT_MAX_QDEPTH 80
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#define DEFAULT_Q0_QDEPTH 511 /* We keep 1 large queue for host tx qos */
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#define DEFAULT_TMU3_QDEPTH 127
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#endif /* _TMU_CSR_H_ */
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