upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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52 lines
1.3 KiB
52 lines
1.3 KiB
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
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#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
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#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
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#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
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#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
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#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
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struct crlapb_regs {
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u32 reserved0[74];
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u32 timestamp_ref_ctrl; /* 0x128 */
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u32 reserved0_1[53];
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u32 boot_mode; /* 0x200 */
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u32 reserved1[26];
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};
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
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#define ZYNQMP_IOU_SCNTR 0xFF250000
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
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struct iou_scntr {
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u32 counter_control_register;
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u32 reserved0[7];
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u32 base_frequency_id_register;
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};
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#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
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/* Bootmode setting values */
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#define BOOT_MODES_MASK 0x0000000F
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#define SD_MODE 0x00000005
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#define JTAG_MODE 0x00000000
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/* Board version value */
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#define ZYNQMP_CSU_VERSION_SILICON 0x0
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#define ZYNQMP_CSU_VERSION_EP108 0x1
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#define ZYNQMP_CSU_VERSION_QEMU 0x3
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#endif /* _ASM_ARCH_HARDWARE_H */
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