upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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362 lines
9.3 KiB
362 lines
9.3 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#include <spd_sdram.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../common/pq-mds-pib.h"
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#endif
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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{0, 3, 1, 0, 1}, /* TxD0 */
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{0, 4, 1, 0, 1}, /* TxD1 */
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{0, 5, 1, 0, 1}, /* TxD2 */
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{0, 6, 1, 0, 1}, /* TxD3 */
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{1, 6, 1, 0, 3}, /* TxD4 */
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{1, 7, 1, 0, 1}, /* TxD5 */
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{1, 9, 1, 0, 2}, /* TxD6 */
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{1, 10, 1, 0, 2}, /* TxD7 */
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{0, 9, 2, 0, 1}, /* RxD0 */
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{0, 10, 2, 0, 1}, /* RxD1 */
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{0, 11, 2, 0, 1}, /* RxD2 */
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{0, 12, 2, 0, 1}, /* RxD3 */
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{0, 13, 2, 0, 1}, /* RxD4 */
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{1, 1, 2, 0, 2}, /* RxD5 */
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{1, 0, 2, 0, 2}, /* RxD6 */
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{1, 4, 2, 0, 2}, /* RxD7 */
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{0, 7, 1, 0, 1}, /* TX_EN */
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{0, 8, 1, 0, 1}, /* TX_ER */
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{0, 15, 2, 0, 1}, /* RX_DV */
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{0, 16, 2, 0, 1}, /* RX_ER */
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{0, 0, 2, 0, 1}, /* RX_CLK */
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{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
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{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
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/* GETH2 */
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{0, 17, 1, 0, 1}, /* TxD0 */
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{0, 18, 1, 0, 1}, /* TxD1 */
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{0, 19, 1, 0, 1}, /* TxD2 */
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{0, 20, 1, 0, 1}, /* TxD3 */
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{1, 2, 1, 0, 1}, /* TxD4 */
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{1, 3, 1, 0, 2}, /* TxD5 */
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{1, 5, 1, 0, 3}, /* TxD6 */
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{1, 8, 1, 0, 3}, /* TxD7 */
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{0, 23, 2, 0, 1}, /* RxD0 */
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{0, 24, 2, 0, 1}, /* RxD1 */
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{0, 25, 2, 0, 1}, /* RxD2 */
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{0, 26, 2, 0, 1}, /* RxD3 */
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{0, 27, 2, 0, 1}, /* RxD4 */
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{1, 12, 2, 0, 2}, /* RxD5 */
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{1, 13, 2, 0, 3}, /* RxD6 */
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{1, 11, 2, 0, 2}, /* RxD7 */
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{0, 21, 1, 0, 1}, /* TX_EN */
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{0, 22, 1, 0, 1}, /* TX_ER */
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{0, 29, 2, 0, 1}, /* RX_DV */
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{0, 30, 2, 0, 1}, /* RX_ER */
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{0, 31, 2, 0, 1}, /* RX_CLK */
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{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
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{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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{5, 0, 1, 0, 2}, /* UART2_SOUT */
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{5, 1, 2, 0, 3}, /* UART2_CTS */
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{5, 2, 1, 0, 1}, /* UART2_RTS */
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{5, 3, 2, 0, 2}, /* UART2_SIN */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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int board_early_init_f(void)
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{
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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/* Enable flash write */
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bcsr[0xa] &= ~0x04;
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/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
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if (REVID_MAJOR(immr->sysconf.spridr) == 2)
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bcsr[0xe] = 0x30;
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/* Enable second UART */
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bcsr[0x9] &= ~0x01;
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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static int sdram_init(unsigned int base);
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize DDR ECC byte
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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msize += sdram_init(msize * 1024 * 1024);
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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#ifdef CONFIG_DDR_II
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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#else
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im->ddr.csbnds[0].csbnds = 0x00000007;
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im->ddr.csbnds[1].csbnds = 0x0008000f;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
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im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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#endif
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif /*!CONFIG_SYS_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC8360EMDS\n");
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return 0;
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}
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/*
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* if MPC8360EMDS is soldered with SDRAM
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*/
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#ifdef CONFIG_SYS_LB_SDRAM
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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static int sdram_init(unsigned int base)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile fsl_lbus_t *lbc = &immap->lbus;
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const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
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int rem = base % sdram_size;
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uint *sdram_addr;
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/* window base address should be aligned to the window size */
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if (rem)
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base = base - rem + sdram_size;
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sdram_addr = (uint *)base;
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/*
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* Setup SDRAM Base and Option Registers
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*/
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immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
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immap->lbus.bank[2].or = CONFIG_SYS_OR2;
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immap->sysconf.lblaw[2].bar = base;
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immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
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/*setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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/*
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* We need do 8 times auto refresh operation.
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*/
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
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asm("sync");
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*sdram_addr = 0xff; /* 1 times */
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udelay(100);
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*sdram_addr = 0xff; /* 2 times */
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udelay(100);
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*sdram_addr = 0xff; /* 3 times */
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udelay(100);
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*sdram_addr = 0xff; /* 4 times */
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udelay(100);
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*sdram_addr = 0xff; /* 5 times */
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udelay(100);
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*sdram_addr = 0xff; /* 6 times */
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udelay(100);
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*sdram_addr = 0xff; /* 7 times */
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udelay(100);
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*sdram_addr = 0xff; /* 8 times */
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udelay(100);
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/* Mode register write operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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asm("sync");
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*(sdram_addr + 0xcc) = 0xff;
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udelay(100);
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/* Normal operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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/*
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* In non-aligned case we don't [normally] use that memory because
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* there is a hole.
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*/
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if (rem)
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return 0;
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return CONFIG_SYS_LBC_SDRAM_SIZE;
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}
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#else
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static int sdram_init(unsigned int base) { return 0; }
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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/*
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* mpc8360ea pb mds errata 2: RGMII timing
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* if on mpc8360ea rev. 2.1,
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* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
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*/
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if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
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(REVID_MINOR(immr->sysconf.spridr) == 1)) {
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int nodeoffset;
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const char *prop;
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int path;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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#if defined(CONFIG_HAS_ETH0)
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/* fixup UCC 1 if using rgmii-id mode */
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prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
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if (prop) {
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path = fdt_path_offset(blob, prop);
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prop = fdt_getprop(blob, path,
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"phy-connection-type", 0);
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if (prop && (strcmp(prop, "rgmii-id") == 0))
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fdt_setprop(blob, path,
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"phy-connection-type",
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"rgmii-rxid",
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sizeof("rgmii-rxid"));
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}
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#endif
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#if defined(CONFIG_HAS_ETH1)
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/* fixup UCC 2 if using rgmii-id mode */
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prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
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if (prop) {
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path = fdt_path_offset(blob, prop);
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prop = fdt_getprop(blob, path,
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"phy-connection-type", 0);
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if (prop && (strcmp(prop, "rgmii-id") == 0))
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fdt_setprop(blob, path,
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"phy-connection-type",
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"rgmii-rxid",
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sizeof("rgmii-rxid"));
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}
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#endif
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}
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}
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}
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#endif
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