upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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281 lines
8.4 KiB
281 lines
8.4 KiB
/*
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* Palm Treo 680 configuration file
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*
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* Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
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*
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* This file is released under the terms of GPL v2 and any later version.
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* See the file COPYING in the root directory of the source tree for details.
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA27X
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#define CONFIG_PALMTREO680
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#define CONFIG_MACH_TYPE MACH_TYPE_TREO680
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#define CONFIG_SYS_MALLOC_LEN (4096*1024)
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#define CONFIG_LZMA
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/*
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* Serial Console Configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_CONS_INDEX 3
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/* we have nand (although technically nand *is* flash...) */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_LCD
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/* #define CONFIG_KEYBOARD */ /* TODO */
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/*
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* Bootloader Components Configuration
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_SOURCE
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#undef CONFIG_CMD_XIMG
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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/*
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* MMC Card Configuration
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* LCD
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*/
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#ifdef CONFIG_LCD
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#define CONFIG_PXA_LCD
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#define CONFIG_ACX544AKN
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#define CONFIG_LCD_LOGO
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#define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
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#define LCD_BPP LCD_COLOR16
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#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */
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#define CONFIG_CMD_BMP
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#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */
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#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
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#endif
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/*
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* KGDB
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*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
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#endif
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/*
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* HUSH Shell Configuration
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ "
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#else
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
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/*
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* Stack sizes
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000
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#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000
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#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A
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#define CONFIG_SYS_GAFR1_L_VAL 0x60000002
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#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959
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#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA
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#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08
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#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF
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#define CONFIG_SYS_GAFR3_U_VAL 0x00001401
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#define CONFIG_SYS_GPCR0_VAL 0x1FF80400
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#define CONFIG_SYS_GPCR1_VAL 0x03003FC1
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#define CONFIG_SYS_GPCR2_VAL 0x01C1E000
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#define CONFIG_SYS_GPCR3_VAL 0x01C1E000
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#define CONFIG_SYS_GPDR0_VAL 0xCFF90400
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#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1
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#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF
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#define CONFIG_SYS_GPDR3_VAL 0x0069FF81
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#define CONFIG_SYS_GPSR0_VAL 0x02000018
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#define CONFIG_SYS_GPSR1_VAL 0x00000000
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#define CONFIG_SYS_GPSR2_VAL 0x000C0000
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#define CONFIG_SYS_GPSR3_VAL 0x00080000
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#define CONFIG_SYS_PSSR_VAL 0x30
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/*
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* Clock settings
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*/
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#define CONFIG_SYS_CKEN 0x01ffffff
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#define CONFIG_SYS_CCCR 0x02000210
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/*
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* Memory settings
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*/
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#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
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#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
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#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
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#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
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#define CONFIG_SYS_MDREFR_VAL 0x201fa031
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#define CONFIG_SYS_MDMRS_VAL 0x00320032
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x40044004
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#define CONFIG_SYS_MECR_VAL 0x00000003
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#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
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#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
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#define CONFIG_SYS_MCATT0_VAL 0x0001c391
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#define CONFIG_SYS_MCATT1_VAL 0x0001c391
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#define CONFIG_SYS_MCIO0_VAL 0x00014611
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#define CONFIG_SYS_MCIO1_VAL 0x0001c391
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/*
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* USB
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*/
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#define CONFIG_USB_DEVICE
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#define CONFIG_USB_TTY
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#define CONFIG_USB_DEV_PULLUP_GPIO 114
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/*
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* SPL
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*/
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#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */
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#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */
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#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
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#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */
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#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */
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/*
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* NAND
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*/
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#define CONFIG_NAND_DOCG4
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
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#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
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#define CONFIG_BITREVERSE /* needed by docg4 driver */
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#define CONFIG_BCH /* needed by docg4 driver */
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/*
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* IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It
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* will be rounded up to the next 64k boundary (the spl flash block size), so it
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* does not have to be exact, but you must ensure that it is not less than the
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* actual image size, or it may fail to boot (bricked phone)!
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* (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
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*/
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
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/*
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* This is the byte offset into the flash at which the concatenated spl + u-boot
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* image is placed. It must be at the start of a block (256k boundary). Blocks
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* 0 - 5 are write-protected, so we start at block 6.
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */
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/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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/* passed to linker by Makefile as arg to -Ttext option */
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#define CONFIG_SYS_TEXT_BASE 0xa0000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */
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/*
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* environment
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*/
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_BUILD_ENVCRC
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#define CONFIG_ENV_SIZE 0x200
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"stdin=usbtty\0" \
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"stdout=usbtty\0" \
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"stderr=usbtty"
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#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
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ip=192.168.11.102:::255.255.255.0:treo:usb0"
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#define CONFIG_BOOTDELAY 3
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#if 0 /* example: try 2nd mmc partition, then nand */
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan; " \
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"if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \
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"bootm 0xa1000000; " \
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"elif nand read 0xa1000000 0x280000 0x240000; then " \
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"bootm 0xa1000000; " \
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"fi; "
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#endif
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/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
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#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_ICACHE_OFF
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#endif /* __CONFIG_H */
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