upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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423 lines
11 KiB
423 lines
11 KiB
/*
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* PCIe driver for Marvell MVEBU SoCs
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*
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* Based on Barebox drivers/pci/pci-mvebu.c
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*
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* Ported to U-Boot by:
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* Anton Schubert <anton.schubert@gmx.de>
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* Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/mbus.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* PCIe unit register offsets */
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#define SELECT(x, n) ((x >> n) & 1UL)
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#define PCIE_DEV_ID_OFF 0x0000
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#define PCIE_CMD_OFF 0x0004
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_CAPAB_OFF 0x0060
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#define PCIE_CTRL_STAT_OFF 0x0068
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
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#define PCIE_WIN5_CTRL_OFF 0x1880
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#define PCIE_WIN5_BASE_OFF 0x1884
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#define PCIE_WIN5_REMAP_OFF 0x188c
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#define PCIE_CONF_ADDR_OFF 0x18f8
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#define PCIE_CONF_ADDR_EN BIT(31)
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#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
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#define PCIE_CONF_ADDR(dev, reg) \
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(PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
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PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_MASK_ENABLE_INTS (0xf << 24)
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE BIT(0)
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_BUS (0xff << 8)
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#define PCIE_STAT_DEV (0x1f << 16)
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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struct resource {
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u32 start;
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u32 end;
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};
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struct mvebu_pcie {
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struct pci_controller hose;
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char *name;
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void __iomem *base;
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void __iomem *membase;
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struct resource mem;
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void __iomem *iobase;
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u32 port;
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u32 lane;
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u32 lane_mask;
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pci_dev_t dev;
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};
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#define to_pcie(_hc) container_of(_hc, struct mvebu_pcie, pci)
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/*
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* MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
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* into SoCs address space. Each controller will map 32M of MEM
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* and 64K of I/O space when registered.
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*/
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static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
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#define PCIE_MEM_SIZE (32 << 20)
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#if defined(CONFIG_ARMADA_38X)
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#define PCIE_BASE(if) \
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((if) == 0 ? \
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MVEBU_REG_PCIE_BASE + 0x40000 : \
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MVEBU_REG_PCIE_BASE + 0x4000 * (if))
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/*
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* On A38x MV6820 these PEX ports are supported:
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* 0 - Port 0.0
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* 1 - Port 0.1
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* 2 - Port 0.2
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*/
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#define MAX_PEX 3
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static struct mvebu_pcie pcie_bus[MAX_PEX];
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static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
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int *mem_target, int *mem_attr)
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{
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u8 port[] = { 0, 1, 2 };
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u8 lane[] = { 0, 0, 0 };
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u8 target[] = { 8, 4, 4 };
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u8 attr[] = { 0xe8, 0xe8, 0xd8 };
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pcie->port = port[pex_idx];
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pcie->lane = lane[pex_idx];
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*mem_target = target[pex_idx];
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*mem_attr = attr[pex_idx];
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}
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#else
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#define PCIE_BASE(if) \
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((if) < 8 ? \
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(MVEBU_REG_PCIE_BASE + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) : \
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(MVEBU_REG_PCIE_BASE + 0x2000 + ((if) % 8) * 0x40000))
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/*
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* On AXP MV78460 these PEX ports are supported:
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* 0 - Port 0.0
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* 1 - Port 0.1
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* 2 - Port 0.2
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* 3 - Port 0.3
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* 4 - Port 1.0
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* 5 - Port 1.1
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* 6 - Port 1.2
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* 7 - Port 1.3
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* 8 - Port 2.0
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* 9 - Port 3.0
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*/
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#define MAX_PEX 10
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static struct mvebu_pcie pcie_bus[MAX_PEX];
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static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx,
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int *mem_target, int *mem_attr)
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{
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u8 port[] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 3 };
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u8 lane[] = { 0, 1, 2, 3, 0, 1, 2, 3, 0, 0 };
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u8 target[] = { 4, 4, 4, 4, 8, 8, 8, 8, 4, 8 };
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u8 attr[] = { 0xe8, 0xd8, 0xb8, 0x78,
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0xe8, 0xd8, 0xb8, 0x78,
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0xf8, 0xf8 };
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pcie->port = port[pex_idx];
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pcie->lane = lane[pex_idx];
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*mem_target = target[pex_idx];
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*mem_attr = attr[pex_idx];
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}
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#endif
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static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
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{
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u32 val;
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val = readl(pcie->base + PCIE_STAT_OFF);
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return !(val & PCIE_STAT_LINK_DOWN);
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}
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static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_BUS;
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stat |= busno << 8;
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writel(stat, pcie->base + PCIE_STAT_OFF);
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}
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static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_DEV;
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stat |= devno << 16;
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writel(stat, pcie->base + PCIE_STAT_OFF);
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}
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static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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return (stat & PCIE_STAT_BUS) >> 8;
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}
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static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
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{
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u32 stat;
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stat = readl(pcie->base + PCIE_STAT_OFF);
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return (stat & PCIE_STAT_DEV) >> 16;
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}
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static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
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{
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return container_of(hose, struct mvebu_pcie, hose);
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}
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static int mvebu_pcie_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 *val)
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{
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struct mvebu_pcie *pcie = hose_to_pcie(hose);
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int local_bus = PCI_BUS(pcie->dev);
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int local_dev = PCI_DEV(pcie->dev);
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u32 reg;
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/* Only allow one other device besides the local one on the local bus */
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if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
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if (local_dev == 0 && PCI_DEV(dev) != 1) {
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/*
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* If local dev is 0, the first other dev can
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* only be 1
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*/
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*val = 0xffffffff;
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return 1;
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} else if (local_dev != 0 && PCI_DEV(dev) != 0) {
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/*
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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*val = 0xffffffff;
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return 1;
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}
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}
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/* write address */
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reg = PCIE_CONF_ADDR(dev, offset);
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writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
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*val = readl(pcie->base + PCIE_CONF_DATA_OFF);
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return 0;
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}
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static int mvebu_pcie_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 val)
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{
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struct mvebu_pcie *pcie = hose_to_pcie(hose);
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int local_bus = PCI_BUS(pcie->dev);
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int local_dev = PCI_DEV(pcie->dev);
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/* Only allow one other device besides the local one on the local bus */
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if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) {
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if (local_dev == 0 && PCI_DEV(dev) != 1) {
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/*
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* If local dev is 0, the first other dev can
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* only be 1
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*/
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return 1;
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} else if (local_dev != 0 && PCI_DEV(dev) != 0) {
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/*
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* If local dev is not 0, the first other dev can
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* only be 0
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*/
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return 1;
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}
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}
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writel(PCIE_CONF_ADDR(dev, offset), pcie->base + PCIE_CONF_ADDR_OFF);
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writel(val, pcie->base + PCIE_CONF_DATA_OFF);
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return 0;
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}
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
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{
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const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
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u32 size;
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int i;
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/* First, disable and clear BARs and windows. */
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for (i = 1; i < 3; i++) {
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writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
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writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
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}
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for (i = 0; i < 5; i++) {
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writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
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}
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writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
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writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
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writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
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/* Setup windows for DDR banks. Count total DDR size on the fly. */
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000,
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pcie->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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pcie->base + PCIE_WIN04_CTRL_OFF(i));
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size += cs->size;
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}
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/* Round up 'size' to the nearest power of two. */
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if ((size & (size - 1)) != 0)
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size = 1 << fls(size);
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/* Setup BAR[1] to all DRAM banks. */
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writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
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writel(((size - 1) & 0xffff0000) | 0x1,
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pcie->base + PCIE_BAR_CTRL_OFF(1));
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}
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void pci_init_board(void)
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{
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int mem_target, mem_attr, i;
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int bus = 0;
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u32 reg;
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u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4);
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/* Check SoC Control Power State */
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debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n",
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__func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1),
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SELECT(soc_ctrl, 2));
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for (i = 0; i < MAX_PEX; i++) {
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struct mvebu_pcie *pcie = &pcie_bus[i];
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struct pci_controller *hose = &pcie->hose;
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/* Get port number, lane number and memory target / attr */
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mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr);
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/* Don't read at all from pci registers if port power is down */
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if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) {
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i += 3;
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debug("%s: skipping port %d\n", __func__, pcie->port);
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continue;
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}
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pcie->base = (void __iomem *)PCIE_BASE(i);
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/* Check link and skip ports that have no link */
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if (!mvebu_pcie_link_up(pcie)) {
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debug("%s: PCIe %d.%d - down\n", __func__,
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pcie->port, pcie->lane);
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continue;
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}
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debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
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pcie->port, pcie->lane, (u32)pcie->base);
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/* Read Id info and local bus/dev */
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debug("direct conf read %08x, local bus %d, local dev %d\n",
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readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
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mvebu_pcie_get_local_dev_nr(pcie));
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mvebu_pcie_set_local_bus_nr(pcie, bus);
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mvebu_pcie_set_local_dev_nr(pcie, 0);
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pcie->dev = PCI_BDF(bus, 0, 0);
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pcie->mem.start = (u32)mvebu_pcie_membase;
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pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
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mvebu_pcie_membase += PCIE_MEM_SIZE;
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if (mvebu_mbus_add_window_by_id(mem_target, mem_attr,
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(phys_addr_t)pcie->mem.start,
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PCIE_MEM_SIZE)) {
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printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
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(u32)pcie->mem.start, PCIE_MEM_SIZE);
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}
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/* Setup windows and configure host bridge */
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mvebu_pcie_setup_wins(pcie);
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/* Master + slave enable. */
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reg = readl(pcie->base + PCIE_CMD_OFF);
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reg |= PCI_COMMAND_MEMORY;
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reg |= PCI_COMMAND_MASTER;
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reg |= BIT(10); /* disable interrupts */
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writel(reg, pcie->base + PCIE_CMD_OFF);
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/* Setup U-Boot PCI Controller */
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hose->first_busno = 0;
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hose->current_busno = bus;
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/* PCI memory space */
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pci_set_region(hose->regions + 0, pcie->mem.start,
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pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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0, 0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 2;
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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mvebu_pcie_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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mvebu_pcie_write_config_dword);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* Set BAR0 to internal registers */
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writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
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writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
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bus = hose->last_busno + 1;
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}
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}
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