upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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86 lines
1.2 KiB
86 lines
1.2 KiB
#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__
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#define __ASM_AVR32_ARCH_GPIO_IMPL_H__
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/* Register offsets */
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struct gpio_regs {
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u32 GPER;
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u32 GPERS;
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u32 GPERC;
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u32 GPERT;
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u32 PMR0;
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u32 PMR0S;
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u32 PMR0C;
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u32 PMR0T;
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u32 PMR1;
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u32 PMR1S;
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u32 PMR1C;
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u32 PMR1T;
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u32 __reserved0[4];
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u32 ODER;
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u32 ODERS;
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u32 ODERC;
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u32 ODERT;
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u32 OVR;
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u32 OVRS;
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u32 OVRC;
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u32 OVRT;
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u32 PVR;
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u32 __reserved_PVRS;
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u32 __reserved_PVRC;
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u32 __reserved_PVRT;
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u32 PUER;
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u32 PUERS;
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u32 PUERC;
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u32 PUERT;
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u32 PDER;
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u32 PDERS;
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u32 PDERC;
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u32 PDERT;
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u32 IER;
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u32 IERS;
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u32 IERC;
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u32 IERT;
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u32 IMR0;
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u32 IMR0S;
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u32 IMR0C;
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u32 IMR0T;
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u32 IMR1;
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u32 IMR1S;
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u32 IMR1C;
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u32 IMR1T;
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u32 GFER;
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u32 GFERS;
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u32 GFERC;
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u32 GFERT;
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u32 IFR;
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u32 __reserved_IFRS;
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u32 IFRC;
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u32 __reserved_IFRT;
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u32 ODMER;
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u32 ODMERS;
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u32 ODMERC;
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u32 ODMERT;
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u32 __reserved1[4];
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u32 ODCR0;
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u32 ODCR0S;
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u32 ODCR0C;
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u32 ODCR0T;
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u32 ODCR1;
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u32 ODCR1S;
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u32 ODCR1C;
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u32 ODCR1T;
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u32 __reserved2[4];
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u32 OSRR0;
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u32 OSRR0S;
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u32 OSRR0C;
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u32 OSRR0T;
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u32 __reserved3[8];
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u32 STER;
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u32 STERS;
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u32 STERC;
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u32 STERT;
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u32 __reserved4[35];
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u32 VERSION;
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};
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#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */
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