upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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131 lines
3.4 KiB
131 lines
3.4 KiB
/**
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* Copyright 2013 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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* Po Liu <Po.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the board-specific CPLD used on some Freescale
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* reference boards.
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*
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* The following macros need to be defined:
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*
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* CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
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* CPLD register map
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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/**
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* Set the boot bank to the alternate bank
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*/
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void cpld_set_altbank(u8 banksel)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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u8 reg11;
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reg11 = in_8(&cpld_data->flhcsr);
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switch (banksel) {
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case 1:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
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break;
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case 2:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
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break;
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case 3:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
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break;
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case 4:
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out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
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| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
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break;
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default:
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printf("Invalid value! [1-4]\n");
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return;
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}
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udelay(100);
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do_reset(NULL, 0, 0, NULL);
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}
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/**
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* Set the boot bank to the default bank
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*/
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void cpld_set_defbank(void)
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{
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cpld_set_altbank(4);
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}
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
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printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
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printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
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printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
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printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
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printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
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printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
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printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
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printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
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printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
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printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
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printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
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printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
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printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
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printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
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printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
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putc('\n');
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}
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#endif
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int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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unsigned char value;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (!strcmp(argv[2], "altbank") && argv[3]) {
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value = (u8)simple_strtoul(argv[3], NULL, 16);
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cpld_set_altbank(value);
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} else if (!argv[2])
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cpld_set_defbank();
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else
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cmd_usage(cmdtp);
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else
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rc = cmd_usage(cmdtp);
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return rc;
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}
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U_BOOT_CMD(
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cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
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"Reset the board using the CPLD sequencer",
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"reset - hard reset to default bank 4\n"
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"cpld_cmd reset altbank [bank]- reset to alternate bank\n"
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" - [bank] bank value select 1-4\n"
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" - bank 1 on the flash 0x0000000~0x0ffffff\n"
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" - bank 2 on the flash 0x1000000~0x1ffffff\n"
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" - bank 3 on the flash 0x2000000~0x2ffffff\n"
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" - bank 4 on the flash 0x3000000~0x3ffffff\n"
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#ifdef DEBUG
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"cpld_cmd dump - display the CPLD registers\n"
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#endif
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);
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