upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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509 lines
11 KiB
509 lines
11 KiB
/*
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* Copyright (C) 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <lcd.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/adc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/watchdog.h>
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#include <libtizen.h>
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#include <ld9040.h>
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#include <power/pmic.h>
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#include <usb/s3c_udc.h>
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#include <asm/arch/cpu.h>
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#include <power/max8998_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct exynos4_gpio_part1 *gpio1;
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struct exynos4_gpio_part2 *gpio2;
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unsigned int board_rev;
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u32 get_board_rev(void)
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{
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return board_rev;
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}
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static int get_hwrev(void)
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{
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return board_rev & 0xFF;
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}
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static void init_pmic_lcd(void);
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int power_init_board(void)
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{
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int ret;
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ret = pmic_init(I2C_5);
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if (ret)
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return ret;
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init_pmic_lcd();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
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get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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static unsigned short get_adc_value(int channel)
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{
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struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
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unsigned short ret = 0;
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unsigned int reg;
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unsigned int loop = 0;
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writel(channel & 0xF, &adc->adcmux);
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writel((1 << 14) | (49 << 6), &adc->adccon);
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writel(1000 & 0xffff, &adc->adcdly);
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writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
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udelay(10);
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writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
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udelay(10);
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do {
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udelay(1);
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reg = readl(&adc->adccon);
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} while (!(reg & (1 << 15)) && (loop++ < 1000));
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ret = readl(&adc->adcdat0) & 0xFFF;
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return ret;
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}
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static int adc_power_control(int on)
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{
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int ret;
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struct pmic *p = pmic_get("MAX8998_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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ret = pmic_set_output(p,
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MAX8998_REG_ONOFF1,
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MAX8998_LDO4, !!on);
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return ret;
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}
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static unsigned int get_hw_revision(void)
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{
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int hwrev, mode0, mode1;
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adc_power_control(1);
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mode0 = get_adc_value(1); /* HWREV_MODE0 */
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mode1 = get_adc_value(2); /* HWREV_MODE1 */
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/*
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* XXX Always set the default hwrev as the latest board
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* ADC = (voltage) / 3.3 * 4096
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*/
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hwrev = 3;
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#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
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if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
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hwrev = 0x0; /* 0.01V 0.01V */
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if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
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hwrev = 0x1; /* 610mV 0.01V */
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if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
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hwrev = 0x2; /* 1.16V 0.01V */
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if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
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hwrev = 0x3; /* 1.79V 0.01V */
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#undef IS_RANGE
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debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
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adc_power_control(0);
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return hwrev;
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}
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static void check_hw_revision(void)
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{
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int hwrev;
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hwrev = get_hw_revision();
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board_rev |= hwrev;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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puts("Board:\tUniversal C210\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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int err;
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switch (get_hwrev()) {
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case 0:
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/*
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* Set the low to enable LDO_EN
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* But when you use the test board for eMMC booting
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* you should set it HIGH since it removes the inverter
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*/
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/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
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s5p_gpio_direction_output(&gpio1->e3, 6, 0);
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break;
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default:
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/*
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* Default reset state is High and there's no inverter
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* But set it as HIGH to ensure
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*/
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/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
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s5p_gpio_direction_output(&gpio1->e1, 3, 1);
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break;
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}
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/*
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* MMC device init
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* mmc0 : eMMC (8-bit buswidth)
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* mmc2 : SD card (4-bit buswidth)
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*/
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err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
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if (err)
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debug("SDMMC0 not configured\n");
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else
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err = s5p_mmc_init(0, 8);
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/* T-flash detect */
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s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
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s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
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/*
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* Check the T-flash detect pin
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* GPX3[4] T-flash detect pin
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*/
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if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
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err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
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if (err)
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debug("SDMMC2 not configured\n");
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else
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err = s5p_mmc_init(2, 4);
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}
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return err;
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}
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#endif
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#ifdef CONFIG_USB_GADGET
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static int s5pc210_phy_control(int on)
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{
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int ret = 0;
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struct pmic *p = pmic_get("MAX8998_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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if (on) {
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ret |= pmic_set_output(p,
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MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
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MAX8998_SAFEOUT1, LDO_ON);
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ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
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MAX8998_LDO3, LDO_ON);
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ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
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MAX8998_LDO8, LDO_ON);
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} else {
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ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
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MAX8998_LDO8, LDO_OFF);
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ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
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MAX8998_LDO3, LDO_OFF);
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ret |= pmic_set_output(p,
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MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
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MAX8998_SAFEOUT1, LDO_OFF);
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}
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if (ret) {
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puts("MAX8998 LDO setting error!\n");
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return -1;
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}
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return 0;
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}
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struct s3c_plat_otg_data s5pc210_otg_data = {
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.phy_control = s5pc210_phy_control,
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.regs_phy = EXYNOS4_USBPHY_BASE,
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.regs_otg = EXYNOS4_USBOTG_BASE,
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.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
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.usb_flags = PHY0_SLEEP,
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};
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#endif
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int board_early_init_f(void)
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{
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wdt_stop();
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return 0;
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}
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#ifdef CONFIG_SOFT_SPI
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static void soft_spi_init(void)
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{
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gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
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CONFIG_SOFT_SPI_MODE & SPI_CPOL);
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gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
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gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
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gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
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!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
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!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
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SPI_SCL(1);
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gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
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CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
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!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void universal_spi_scl(int bit)
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{
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gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
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}
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void universal_spi_sda(int bit)
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{
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gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
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}
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int universal_spi_read(void)
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{
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return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
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}
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#endif
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static void init_pmic_lcd(void)
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{
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unsigned char val;
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int ret = 0;
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struct pmic *p = pmic_get("MAX8998_PMIC");
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if (!p)
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return;
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if (pmic_probe(p))
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return;
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/* LDO7 1.8V */
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val = 0x02; /* (1800 - 1600) / 100; */
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ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
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/* LDO17 3.0V */
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val = 0xe; /* (3000 - 1600) / 100; */
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ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
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/* Disable unneeded regulators */
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/*
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* ONOFF1
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* Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
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* LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
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*/
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val = 0xB9;
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ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
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/* ONOFF2
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* LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
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* LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
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*/
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val = 0x50;
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ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
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/* ONOFF3
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* LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
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* EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
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*/
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val = 0x00;
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ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
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if (ret)
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puts("LCD pmic initialisation error!\n");
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}
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void exynos_cfg_lcd_gpio(void)
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{
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unsigned int i, f3_end = 4;
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for (i = 0; i < 8; i++) {
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/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
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s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
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s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
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s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
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/* pull-up/down disable */
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s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
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s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
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s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
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/* drive strength to max (24bit) */
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s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
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s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
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s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
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s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
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s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
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s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
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}
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for (i = 0; i < f3_end; i++) {
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/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
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s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
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/* pull-up/down disable */
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s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
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/* drive strength to max (24bit) */
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s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
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s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
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}
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/* gpio pad configuration for LCD reset. */
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s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
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spi_init();
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}
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void exynos_reset_lcd(void)
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{
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s5p_gpio_set_value(&gpio2->y4, 5, 1);
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udelay(10000);
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s5p_gpio_set_value(&gpio2->y4, 5, 0);
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udelay(10000);
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s5p_gpio_set_value(&gpio2->y4, 5, 1);
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udelay(100);
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}
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void exynos_lcd_power_on(void)
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{
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struct pmic *p = pmic_get("MAX8998_PMIC");
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if (!p)
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return;
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if (pmic_probe(p))
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return;
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pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
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pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
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}
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vidinfo_t panel_info = {
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.vl_freq = 60,
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.vl_col = 480,
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.vl_row = 800,
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.vl_width = 480,
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.vl_height = 800,
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.vl_clkp = CONFIG_SYS_HIGH,
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.vl_hsp = CONFIG_SYS_HIGH,
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.vl_vsp = CONFIG_SYS_HIGH,
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.vl_dp = CONFIG_SYS_HIGH,
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.vl_bpix = 5, /* Bits per pixel */
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/* LD9040 LCD Panel */
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.vl_hspw = 2,
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.vl_hbpd = 16,
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.vl_hfpd = 16,
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.vl_vspw = 2,
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.vl_vbpd = 8,
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.vl_vfpd = 8,
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.vl_cmd_allow_len = 0xf,
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.win_id = 0,
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.dual_lcd_enabled = 0,
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.init_delay = 0,
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.power_on_delay = 10000,
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.reset_delay = 10000,
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.interface_mode = FIMD_RGB_INTERFACE,
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.mipi_enabled = 0,
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};
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void exynos_cfg_ldo(void)
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{
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ld9040_cfg_ldo();
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}
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void exynos_enable_ldo(unsigned int onoff)
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{
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ld9040_enable_ldo(onoff);
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}
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void init_panel_info(vidinfo_t *vid)
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{
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vid->logo_on = 1;
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vid->resolution = HD_RESOLUTION;
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vid->rgb_mode = MODE_RGB_P;
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#ifdef CONFIG_TIZEN
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get_tizen_logo_info(vid);
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#endif
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/* for LD9040. */
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vid->pclk_name = 1; /* MPLL */
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vid->sclk_div = 1;
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setenv("lcdinfo", "lcd=ld9040");
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}
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int board_init(void)
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{
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gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
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gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
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gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
#ifdef CONFIG_SOFT_SPI
|
|
soft_spi_init();
|
|
#endif
|
|
check_hw_revision();
|
|
printf("HW Revision:\t0x%x\n", board_rev);
|
|
|
|
return 0;
|
|
}
|
|
|